/* apedefs.h */ /* Some defs that can be used to print the state of the ape */ struct apedtype { char *name; int loc; }; struct apedtype apedefs[]= { "MODE_REG ", 0x100, /* Operational mode control */ "ACONFIG_REG ", 0x102, /* Configuration reg. */ "ERROR_REG_MASK ", 0x104, /* Mask for error reg. */ "ERROR_REG ", 0x106, /* State/error reg. */ "TCLP0_RCELL ", 0x108, /* Total CLP 0 cells recvd */ "TCLP1_RCELL ", 0x10a, /* Total CLP 1 cells recvd */ "THB_ER_CELL ", 0x10c, /* Total cells w/ hdr error */ "THB_ER_DC ", 0x10e, /* Total cells discarded */ /* .. for header errors */ "MISROUTE_CELL ", 0x110, /* Misrouted cells */ "TOAM_RCELL ", 0x112, /* OAM recvd w/ PTI = 4,5 */ "TOAM_ER_RCELL ", 0x114, /* # received in error */ "TAH_ER_DC ", 0x116, /* Discards for ATM hdr err */ "TCLP0_TCELL ", 0x118, /* Total CLP 0 cells sent */ "TCLP1_TCELL ", 0x11a, /* Total CLP 1 cells sent */ "TOAM_TCELL ", 0x11c, /* OAM sent w/ PTI = 4, 5 */ "DEBUG_SEL_REG ", 0x11e, /* Debug selection reg. */ "LCI_TABLE_BR ", 0x120, /* LCI table base reg */ "LCI_TABLE_TOP ", 0x122, /* Ptr to top of LCI Table */ "LCI_TABLE_BOT ", 0x124, /* Ptr to bottom of LCI tab */ "PCI_ERROR_MASK ", 0x1f0, /* PCI error mask reg. */ "PCI_ERROR_REG ", 0x1f2, /* PCI error reg. */ "IDLE_CELL_HDR_HI ", 0x12a, /* Contains idle cell hdr */ "IDLE_CELL_HDR_LO ", 0x12c, /* Contains idle cell hdr */ "EXT_MEM_CTL ", 0x130, /* Local bus intf cntl */ "DIAG_REG ", 0x132, /* Injects parity and HEC */ /* .. errors. */ "OAM_MASK ", 0x134, /* PT/CLP for OAM redirects */ "OAM_B1_MASK1 ", 0x136, /* Masks for testing payload*/ "OAM_B1_MASK2 ", 0x138, /* .. for OAM recvs. */ "RCB_OVERRUN0 ", 0x13a, /* AAL1/5 overrun drops. */ "RCB_OVERRUN1 ", 0x13c, /* OAM overrun drops. */ "CERR_CNT ", 0x1d0, /* Count C Errors */ "SERR_COUNT ", 0x1d2, /* Count S Errors */ "T0MQ_MIS_CNT ", 0x1d4, /* # TMQ0 service misses. */ "T1MQ_MIS_CNT ", 0x1d6, /* # TMQ1 service misses. */ "T2MQ_MIS_CNT ", 0x1d8, /* # TMQ2 service misses. */ "T3MQ_MIS_CNT ", 0x1da, /* # TMQ3 service misses. */ "T4MQ_MIS_CNT ", 0x1dc, /* # TMQ4 service misses. */ "T5MQ_MIS_CNT ", 0x1de, /* # TMQ5 service misses. */ "T6MQ_MIS_CNT ", 0x1e0, /* # TMQ6 service misses. */ "T7MQ_MIS_CNT ", 0x1e2, /* # TMQ7 service misses. */ "VP_TABLE_BR ", 0x140, /* VP table base reg */ "TCL_LFDA_HI ", 0x150, /* Trans complete list - */ "TCL_LFDA_LO ", 0x152, /* .. last frame desc addr. */ "TCB_TOP ", 0x154, /* Trans cell buf top addr. */ "TCB_BOT ", 0x156, /* TCB bottom address */ "TCB_RD_PTR ", 0x158, /* TCB read pointer */ "TCB_WR_PTR ", 0x15a, /* TCB write pointer */ "FR_TIMEOUT_VAL ", 0x160, /* Time-out invl setup reg. */ "FRTO_AGE_CNTR_HI ", 0x162, /* 24 bit interval counter */ "FRTO_AGE_CNTR_LO ", 0x164, /* .. used to age frames */ "R5CB_TOP ", 0x166, /* Recv cell buf top addr. */ "R5CB_BOT ", 0x168, /* R5 bottom address */ "R5CB_RD_PTR ", 0x16a, /* R5 read pointer */ "R5CB_WR_PTR ", 0x142, /* R5 write pointer */ "R1CB_TOP ", 0x16c, /* Recv cell buf top addr. */ "R1CB_BOT ", 0x16e, /* R1 bottom address */ "R1CB_RD_PTR ", 0x170, /* R1 read pointer */ "R1CB_WR_PTR ", 0x144, /* R1 write pointer */ "ROCB_TOP ", 0x172, /* Recv cell buf top addr. */ "ROCB_BOT ", 0x174, /* R1 bottom address */ "ROCB_RD_PTR ", 0x176, /* R1 read pointer */ "ROCB_WR_PTR ", 0x146, /* R1 write pointer */ "SRFL_HI ", 0x178, /* Starting recv system */ "SRFL_LO ", 0x17a, /* .. buffer desc. */ "RRL0_LBDA_HI ", 0x180, /* Rcv rdy list 0 last BDA */ "RRL0_LBDA_LO ", 0x182, /* Rcv rdy list 0 last BDA */ "RRL1_LBDA_HI ", 0x184, /* Rcv rdy list 0 last BDA */ "RRL1_LBDA_LO ", 0x186, /* Rcv rdy list 0 last BDA */ "RRL2_LBDA_HI ", 0x188, /* Rcv rdy list 0 last BDA */ "RRL2_LBDA_LO ", 0x18a, /* Rcv rdy list 0 last BDA */ "RRL3_LBDA_HI ", 0x18c, /* Rcv rdy list 0 last BDA */ "RRL3_LBDA_LO ", 0x18e, /* Rcv rdy list 0 last BDA */ "RRL4_LBDA_HI ", 0x190, /* Rcv rdy list 0 last BDA */ "RRL4_LBDA_LO ", 0x192, /* Rcv rdy list 0 last BDA */ "RRL5_LBDA_HI ", 0x194, /* Rcv rdy list 0 last BDA */ "RRL5_LBDA_LO ", 0x196, /* Rcv rdy list 0 last BDA */ "RRL6_LBDA_HI ", 0x198, /* Rcv rdy list 0 last BDA */ "RRL6_LBDA_LO ", 0x19a, /* Rcv rdy list 0 last BDA */ "RRL7_LBDA_HI ", 0x19c, /* Rcv rdy list 0 last BDA */ "RRL7_LBDA_LO ", 0x19e, /* Rcv rdy list 0 last BDA */ "TMQ_CFG_0 ", 0x1a0, /* Traffic mgt rate reg 0 */ "TMQ_CFG_1 ", 0x1a2, /* Traffic mgt rate reg 1 */ "TMQ_CFG_2 ", 0x1a4, /* Traffic mgt rate reg 2 */ "TMQ_CFG_3 ", 0x1a6, /* Traffic mgt rate reg 3 */ "TMQ_CFG_4 ", 0x1a8, /* Traffic mgt rate reg 4 */ "TMQ_CFG_5 ", 0x1aa, /* Traffic mgt rate reg 5 */ "TMQ_CFG_6 ", 0x1ac, /* Traffic mgt rate reg 6 */ "TMQ_CFG_7 ", 0x1ae, /* Traffic mgt rate reg 7 */ "T5RQ_BASE ", 0x1b0, /* AAL5 TRQ Base reg. */ "T5RQ_TOP ", 0x1b2, /* AAL5 TRQ Top reg. */ "T5RQ_BOT ", 0x1b4, /* AAL5 TRQ Bot reg. */ "T5RQ_RD_PTR ", 0x1b6, /* AAL5 TRQ Read Pointer. */ "T5RQ_WR_PTR ", 0x1b8, /* AAL5 TRQ Wrt Pointer. */ "T1RQ_BASE ", 0x1ba, /* AAL5 TRQ Base reg. */ "T1RQ_TOP ", 0x1bc, /* AAL5 TRQ Top reg. */ "T1RQ_BOT ", 0x1be, /* AAL5 TRQ Bot reg. */ "T1RQ_RD_PTR ", 0x1c0, /* AAL5 TRQ Read Pointer. */ "T1RQ_WR_PTR ", 0x1c2 /* AAL5 TRQ Wrt Pointer. */ }; #define APE_COUNT (sizeof(apedefs) / sizeof(apedefs[0])) struct apedtype aperegs[]= { "SAP_EXT_REG ", 0x000, "SAP_ADDR_REG ", 0x002, "SAP_DATA_REG ", 0x004, "SAP_DATA_REG_INC ", 0x006, "SISR ", 0x008, "MISR ", 0x00a, "PROM_PAGE_REG ", 0x00c, "AAL1/5 STATUS ", 0x010, "TRQ_AAL1_LC ", 0x014, "TRQ_AAL1_TFDA_H ", 0x016, "TRQ_AAL1_TFDA_L ", 0x018, "TRQ_AAL1_LC ", 0x01a, "TRQ_AAL1_TFDA_H ", 0x01c, "TRQ_AAL1_TFDA_L ", 0x01e, }; #define REG_COUNT (sizeof(aperegs) / sizeof(aperegs[0]))