/* ape25.h */ /* These defines identify elements of the I/O and Control */ /* Spaces of the IBM Atm Protocol Engine 25 (ape25) */ /* Copyright (c) 1996 Robert Geist and James Westall * Clemson University Dept. of Computer Science * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ /* SAP Register addresses with respect to start of IO space */ #define SAP_EXT_ADDR_REG 0 /* High order addr bits */ #define SAP_ADDR_REG 2 /* Low order addr bits */ #define SAP_DATA_PORT 4 /* R/W data value here */ #define SAP_DATA_PORT_INC 6 /* R/W with increment */ #define SISR 8 /* Int status register */ #define MISR 0xa /* SISR Mask register */ #define PROM_PAGE_REG 0xc /* Bios ROM selector */ #define AAL_STATUS 0x10 /* Full TRQ status bits */ #define TRQ_AAL1_LC 0x14 /* LC # for AAL1 writes */ #define TRQ_AAL1_TFDA_HI 0x16 #define TRQ_AAL1_TFDA_LO 0x18 #define TRQ_AAL5_LC 0x1a /* LC # for AAL5 writes */ #define TRQ_AAL5_TFDA_HI 0x1c #define TRQ_AAL5_TFDA_LO 0x1e #define NVRAM_CNTL 0x20 #define ESI_OFFSET 0x10 /* Offset and len in NVRAM */ #define ESI_LEN 6 /* of ESI data. */ /* Base addresses of various regions within the APE 25 */ #define XMIT_PICO_RAM 0x00000000 #define XMIT_PICO_4PORT 0x01000000 #define RECV_PICO_RAM 0x02000000 #define RECV_PICO_4PORT 0x03000000 #define APE25_CONTROL 0x04000000 #define EERAM 0x05000000 #define CONTROL_DATA_RAM 0x08000000 #define RAW_CELL_DEVICE 0x0a000000 #define RIPL_PICO_ROM 0x0c000000 /* Macros for accessing the control registers */ #define WT_CNTLREG(a, b, c) (atm_wtvsap(a, APE25_CONTROL + b, c)) #define RD_CNTLREG(a, b) (atm_rdvsap(a, APE25_CONTROL + b)) /* Macros for accessing XRAM a.k.a. "Control / Data Ram" */ #define WT_XRAM(a, b, c) (atm_wtvsap(a, CONTROL_DATA_RAM + b, c)) #define RD_XRAM(a, b) (atm_rdvsap(a, CONTROL_DATA_RAM + b)) /* Bit definitions for the Mode Register */ #define SOFT_RESET 0x8000 /* 1 => reset the APE 25 */ #define XMIT_ENABLE 0x1000 /* 1 => Enable transmit. */ #define ROCB_ENABLE 0x0400 /* OAM filter enabled. */ #define FRTO_ENABLE 0x0200 /* Frame timeout enabled. */ #define PICO_ENABLE 0x0100 /* Turn on the PICO procs. */ #define INT_WRAP_ENABLE 0x0080 /* Enable internal wrap */ #define EXT_WRAP_DISABLE 0x0040 /* Disable external wrap. */ #define ATOMIC_ENABLE 0x0020 /* ???? */ #define APE_BIG_ENDIAN 0x0010 /* Big endian mode. */ #define TC_SELECT 0x0008 /* Clock Xmit w/ 32Mhz clk */ /* Some "standard" settings for the mode reg. */ #define NORMAL_MODE 0x1740 /* Suggested by the book. */ #define OS2_MODE 0x1049 /* Suggested by the book. */ #define LCLOCK_MODE 0x1748 /* .. w/ local xmit clocking*/ #define RESET_MODE 0x8000 /* For resetting the intf. */ #define INT_WRAP_MODE 0x17c8 /* Interal wrap mode. */ #define EXT_WRAP_MODE 0x1708 /* External wrap mode. */ /* Bit definitions for the SISR */ #define RRL0 0x8000 /* Receive ready bits. */ #define RRL1 0x4000 /* Receive ready bits. */ #define RRL2 0x2000 /* Receive ready bits. */ #define RRL3 0x1000 /* Receive ready bits. */ #define RRL4 0x0800 /* Receive ready bits. */ #define RRL5 0x0400 /* Receive ready bits. */ #define RRL6 0x0200 /* Receive ready bits. */ #define RRL7 0x0100 /* Receive ready bits. */ #define RFL_EMPTY 0x0080 /* Free frame list empty. */ #define RCB_OVERRUN 0x0040 /* Cell buffer overrun. */ #define CBR_INTR 0x0020 /* CBR Interrupt? */ #define APE_ER 0x0010 /* APE Hardware error. */ #define SV_TCL 0x0004 /* Service Xmit Cmplt list */ #define PCI_ERROR 0x0002 /* PCI problem. */ #define TIMER_TICK 0x0001 /* Timer tick. */ /* Control registers -- offsets w/in APE 25 Control */ #define MODE_REG 0x100 /* Operational mode control */ #define ACONFIG_REG 0x102 /* Configuration reg. */ #define ERROR_REG_MASK 0x104 /* Mask for error reg. */ #define ERROR_REG 0x106 /* State/error reg. */ #define TCLP0_RCELL 0x108 /* Total CLP 0 cells recvd */ #define TCLP1_RCELL 0x10a /* Total CLP 1 cells recvd */ #define THB_ER_CELL 0x10c /* Total cells w/ hdr error */ #define THB_ER_DC 0x10e /* Total cells discarded */ /* .. for header errors */ #define MISROUTE_CELL 0x110 /* Misrouted cells */ #define TOAM_RCELL 0x112 /* OAM recvd w/ PTI = 4,5 */ #define TOAM_ER_RCELL 0x114 /* # received in error */ #define TAH_ER_DC 0x116 /* Discards for ATM hdr err */ #define TCLP0_TCELL 0x118 /* Total CLP 0 cells sent */ #define TCLP1_TCELL 0x11a /* Total CLP 1 cells sent */ #define TOAM_TCELL 0x11c /* OAM sent w/ PTI = 4, 5 */ #define DEBUG_SEL_REG 0x11e /* Debug selection reg. */ #define LCI_TABLE_BR 0x120 /* LCI table base reg */ #define LCI_TABLE_TOP 0x122 /* Ptr to top of LCI Table */ #define LCI_TABLE_BOT 0x124 /* Ptr to bottom of LCI tab */ #define PCI_ERROR_MASK 0x1f0 /* PCI error mask reg. */ #define PCI_ERROR_REG 0x1f2 /* PCI error reg. */ #define IDLE_CELL_HDR_HI 0x12a /* Contains idle cell hdr */ #define IDLE_CELL_HDR_LO 0x12c /* Contains idle cell hdr */ #define EXT_MEM_CTL 0x130 /* Local bus intf cntl */ #define DIAG_REG 0x132 /* Injects parity and HEC */ /* .. errors. */ #define OAM_MASK 0x134 /* PT/CLP for OAM redirects */ #define OAM_B1_MASK1 0x136 /* Masks for testing payload*/ #define OAM_B1_MASK2 0x138 /* .. for OAM recvs. */ #define RCB_OVERRUN0 0x13a /* AAL1/5 overrun drops. */ #define RCB_OVERRUN1 0x13c /* OAM overrun drops. */ #define CERR_CNT 0x1d0 /* Count C Errors */ #define SERR_CNT 0x1d2 /* Count S Errors */ #define T0MQ_MIS_CNT 0x1d4 /* # TMQ0 service misses. */ #define T1MQ_MIS_CNT 0x1d6 /* # TMQ1 service misses. */ #define T2MQ_MIS_CNT 0x1d8 /* # TMQ2 service misses. */ #define T3MQ_MIS_CNT 0x1da /* # TMQ3 service misses. */ #define T4MQ_MIS_CNT 0x1dc /* # TMQ4 service misses. */ #define T5MQ_MIS_CNT 0x1de /* # TMQ5 service misses. */ #define T6MQ_MIS_CNT 0x1e0 /* # TMQ6 service misses. */ #define T7MQ_MIS_CNT 0x1e2 /* # TMQ7 service misses. */ #define VP_TABLE_BR 0x140 /* VP table base reg */ #define TCL_LFDA_HI 0x150 /* Trans complete list - */ #define TCL_LFDA_LO 0x152 /* .. last frame desc addr. */ #define TCB_TOP 0x154 /* Trans cell buf top addr. */ #define TCB_BOT 0x156 /* TCB bottom address */ #define TCB_RD_PTR 0x158 /* TCB read pointer */ #define TCB_WR_PTR 0x15a /* TCB write pointer */ #define FR_TIMEOUT_VAL 0x160 /* Time-out invl setup reg. */ #define FRTO_AGE_CNTR_HI 0x162 /* 24 bit interval counter */ #define FRTO_AGE_CNTR_LO 0x164 /* .. used to age frames */ #define R5CB_TOP 0x166 /* Recv cell buf top addr. */ #define R5CB_BOT 0x168 /* R5 bottom address */ #define R5CB_RD_PTR 0x16a /* R5 read pointer */ #define R5CB_WR_PTR 0x142 /* R5 write pointer */ #define R1CB_TOP 0x16c /* Recv cell buf top addr. */ #define R1CB_BOT 0x16e /* R1 bottom address */ #define R1CB_RD_PTR 0x170 /* R1 read pointer */ #define R1CB_WR_PTR 0x144 /* R1 write pointer */ #define ROCB_TOP 0x172 /* Recv cell buf top addr. */ #define ROCB_BOT 0x174 /* R1 bottom address */ #define ROCB_RD_PTR 0x176 /* R1 read pointer */ #define ROCB_WR_PTR 0x146 /* R1 write pointer */ #define SRFL_HI 0x178 /* Starting recv system */ #define SRFL_LO 0x17a /* .. buffer desc. */ #define RRL0_LBDA_HI 0x180 /* Rcv rdy list 0 last BDA */ #define RRL0_LBDA_LO 0x182 /* Rcv rdy list 0 last BDA */ #define RRL1_LBDA_HI 0x184 /* Rcv rdy list 0 last BDA */ #define RRL1_LBDA_LO 0x186 /* Rcv rdy list 0 last BDA */ #define RRL2_LBDA_HI 0x188 /* Rcv rdy list 0 last BDA */ #define RRL2_LBDA_LO 0x18a /* Rcv rdy list 0 last BDA */ #define RRL3_LBDA_HI 0x18c /* Rcv rdy list 0 last BDA */ #define RRL3_LBDA_LO 0x18e /* Rcv rdy list 0 last BDA */ #define RRL4_LBDA_HI 0x190 /* Rcv rdy list 0 last BDA */ #define RRL4_LBDA_LO 0x192 /* Rcv rdy list 0 last BDA */ #define RRL5_LBDA_HI 0x194 /* Rcv rdy list 0 last BDA */ #define RRL5_LBDA_LO 0x196 /* Rcv rdy list 0 last BDA */ #define RRL6_LBDA_HI 0x198 /* Rcv rdy list 0 last BDA */ #define RRL6_LBDA_LO 0x19a /* Rcv rdy list 0 last BDA */ #define RRL7_LBDA_HI 0x19c /* Rcv rdy list 0 last BDA */ #define RRL7_LBDA_LO 0x19e /* Rcv rdy list 0 last BDA */ #define TMQ_CFG_0 0x1a0 /* Traffic mgt rate reg 0 */ #define TMQ_CFG_1 0x1a2 /* Traffic mgt rate reg 1 */ #define TMQ_CFG_2 0x1a4 /* Traffic mgt rate reg 2 */ #define TMQ_CFG_3 0x1a6 /* Traffic mgt rate reg 3 */ #define TMQ_CFG_4 0x1a8 /* Traffic mgt rate reg 4 */ #define TMQ_CFG_5 0x1aa /* Traffic mgt rate reg 5 */ #define TMQ_CFG_6 0x1ac /* Traffic mgt rate reg 6 */ #define TMQ_CFG_7 0x1ae /* Traffic mgt rate reg 7 */ #define T5RQ_BASE 0x1b0 /* AAL5 TRQ Base reg. */ #define T5RQ_TOP 0x1b2 /* AAL5 TRQ Top reg. */ #define T5RQ_BOT 0x1b4 /* AAL5 TRQ Bot reg. */ #define T5RQ_RD_PTR 0x1b6 /* AAL5 TRQ Read Pointer. */ #define T5RQ_WR_PTR 0x1b8 /* AAL5 TRQ Wrt Pointer. */ #define T1RQ_BASE 0x1ba /* AAL5 TRQ Base reg. */ #define T1RQ_TOP 0x1bc /* AAL5 TRQ Top reg. */ #define T1RQ_BOT 0x1be /* AAL5 TRQ Bot reg. */ #define T1RQ_RD_PTR 0x1c0 /* AAL5 TRQ Read Pointer. */ #define T1RQ_WR_PTR 0x1c2 /* AAL5 TRQ Wrt Pointer. */ /* This structure maps the AAL5 LC block */ struct lc5type { short maxsdu; /* Max SDU len. */ short fssfdhi; /* First system start of */ short fssfdlo; /* first frame buf addr. */ short csbdhi; /* Current system buffer */ short csdblo; /* descriptor address. */ short sbl; /* Length of current buf */ short rtuc; /* Recvd total user cells*/ short rcbip; /* Recv calc BIP-16. */ unsigned char ftoc; /* Frame timeout ctr. */ unsigned char aalstate; /* Idle, reasm, or abort */ short rrbl; /* Residual byte count */ /* .. of crnt sys buf. */ short rclp0; /* CLP 0 cells received. */ short rcfchi; /* AAL5 recv CRC. */ short rcfclo; /* */ short csbahi; /* Current sys buf addr. */ short csbalo; /* */ short rsdul; /* Cumulative SDU len. */ unsigned char resvd1; /* Reserved. */ unsigned char rcc; /* # congestion notifies */ unsigned char lcflags; /* OAM, CHM, PME, BLS */ unsigned char rrl; /* RcvRdy List ID for LC */ /* (shifted left 2 bits) */ unsigned char psr; /* Peak sustainable rate */ unsigned char crd; /* Congestion rate div. */ short bts; /* Burst tol. specifier. */ unsigned char ttp; /* Transmit throttling */ /* prescaler. */ unsigned char tcc; /* Transmit cong. count. */ unsigned char msn; /* Mon. cell seq. num. */ unsigned char trc; /* # cells xmitted at */ /* current cong. rate. */ short arthi; /* (20 bits) avg rate */ short artlo; /* */ /* timer. */ unsigned char tpc; /* Transmit prescaling */ /* ..counter. */ unsigned char nfs; /* New frame status. */ short tfp; /* TMQ forward pointer. */ short tcfchi; /* AAL5 xmit CRC. */ short tcfclo; /* */ short tcbip; /* Xmit calc BIP-16. */ unsigned char tbc; /* # buffers assoc with */ /* current xmit frame. */ unsigned char trbc; /* Xmit resid buf count */ short alc; /* AAL5 Control field. */ short tsdul; /* Current SDU length. */ short tscbhi; /* Current buffer addr. */ short tscblo; /* */ short trbl; /* Current resid length. */ short ttuc; /* Total user cells sent.*/ short tclp0; /* CLP 0 cells sent. */ short tflags; /* SOM, lnk stat, TMQ */ short cfdhi; /* Current frame desc. */ short cfdlo; /* */ /* address. */ short lfdhi; /* Last frame desc. addr */ short lfdlo; /* */ short chdr1; /* GFC, VPI, VCI (hi) */ short chdr2; /* VCI (low) PTI, CLP. */ }; /* Receive frame management structures */ #define RBS_STR_FRAME (1<<0) /* 1 => start of new frame */ #define RBS_END_FRAME (1<<1) /* 1 => last buffer of frame */ #define RBS_TIMEOUT (1<<2) /* 1 => assembly timeout. */ #define RBS_SDU_ZLEN (1<<3) /* 1 => frame trailer len = 0 */ #define RBS_OVERFLOW (1<<4) /* 1 => len > max lc sdu len */ #define RBS_CRCERROR (1<<5) /* 1 => AAL5 CRC error. */ #define RBS_MATCHERR (1<<6) /* 1 => AAL5 length mismatch. */ #define RBS_NOFREEBD (1<<7) /* 1 => Free buf list empty. */ #define RBS_LASTCLP (1<<8) /* CLP of last cell in frame. */ #define RBS_LASTPTI (1<<9) /* PTI of last cell in frame. */ /* Common buffer descriptor used by APE 25 and driver for */ /* management of free frames. */ /* The short elements of these structure appear to be out */ /* of order when compared with the book. However they are */ /* not.. Note that the book views the entire structure in */ /* terms of 32 bit words.. Since we operate in a little */ /* endian realm its necessary to re-order elements lying */ /* within a given word. */ struct rbhtype { char *data; /* Address of frame data. */ struct rbhtype *next; /* Address of next header */ short status; /* Buffer status flags. */ short len; /* Length of buffer. */ short control; /* AAL5 CPCS trailer info. */ /* or AAL1 SRTS TSV */ short lci; /* LCI associated w/ buf */ short clp0tuc; /* Cell loss count (OAM only) */ short sdulen; /* Frame len (in 1st buf dsc). */ #ifdef FULL_STACK struct sk_buff *skb; /* Pointer to skb header. */ #endif char *vdata; /* Virtual address of data. */ }; /* Transmit data buffer descriptor structure */ /* These structs are elements of the transmit frame descs. */ struct tdbtype { char *data; /* -> actual data buffer */ short resvd1; /* Reserved and 0. */ short buflen; /* # of bytes in the buffer */ }; /* Transmit frame descriptors.. Used by system and APE25 */ /* to manage pending and complete transmit operations. */ #define MTB 1 /* Max # of transmit bufs / frame */ struct tfdtype { struct tfdtype *next; /* Next tfd */ struct tfdtype *tclnext; /* Next xmit complete tfd */ unsigned char bufcount; /* This tfds buffer count. */ unsigned char prmstat; /* Parms / status byte. */ short lci; /* LCI of buffer. */ unsigned short sdulen; /* Data length. */ unsigned short control; /* Control field. */ struct tdbtype dbds[MTB]; /* Data buffer descriptors. */ struct tdbtype vdbds[MTB];/* Data buffer descriptors. */ #ifdef FULL_STACK struct sk_buff *skb; /* Pointer to skbuff hdr. */ struct atm_vcc *vcc; /* Pointer to vcc. */ #endif }; /**/ /* Peformance measurement data */ struct pmdtype { /* These values here are all acquired via the SISR */ unsigned int intcount[2]; /* Interrupt counter. */ unsigned int intcats[16][2]; /* Interrupts by category. */ unsigned int rclp0[2]; unsigned int rclp1[2]; unsigned int tclp0[2]; unsigned int tclp1[2]; unsigned int roam; unsigned int toam; unsigned int misrt; unsigned int tmqwaits; unsigned int tclwaits; unsigned int tbcwaits; unsigned int tmqmisses[8]; unsigned int lcin[LCI_COUNT]; /* Packets in and out on LC's */ unsigned int lcout[LCI_COUNT]; };