/* ia_fred.h */ /* Copyright (c) 2000 James M. Westall, Dept of Computer Science, * Clemson University, Clemson SC 29634 USA * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * To obtain a copy of the GNU General Public License write to the * Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. * * This software is derived from software developed by the Interphase * corporation and released by them in September 2000. The software * released by Interphase carried the following copyright notice: * * * Copyright (C) 1993 * Interphase Corporation, Dallas, TX 75234 * All Rights Reserved * * This code contains confidential information and trade secrets of * Interphase Corporation which shall not be reproduced or transferred * to other programs or disclosed to others or used for manufacturing * or any other purpose without prior written permission of Interphase * Corporation. Use of copyright notice is precautionary and does not * imply publication or intent thereof. */ /*H * FILE: ia_fred.h * * DESCRIPTION: * This files contains header information for both, the Fragmentation * and the Reassembly, FREDs. * * FUNCTIONS: * EXPORTED: * * STATIC: * * GLOBAL DATA: * */ #ifndef _FRED_H #define _FRED_H /******************************** F-Fred ********************************/ typedef uint_t freg_t; /* * Pre-Atlantic only */ typedef struct _ffred_t { freg_t rq_reg_b0; /* Rate Register, Bank B, Queue 0 */ freg_t rq_reg_b1; /* Rate Register, Bank B, Queue 1 */ freg_t rq_reg_b2; /* Rate Register, Bank B, Queue 2 */ freg_t rq_reg_b3; /* Rate Register, Bank B, Queue 3 */ freg_t rq_reg_a0; /* Rate Register, Bank A, Queue 0 */ freg_t rq_reg_a1; /* Rate Register, Bank A, Queue 1 */ freg_t rq_reg_a2; /* Rate Register, Bank A, Queue 2 */ freg_t rq_reg_a3; /* Rate Register, Bank A, Queue 3 */ uint_t filler1[0x17 - 0x08]; freg_t cmd_reg; /* Command register */ uint_t filler2[0x20 - 0x18]; freg_t cbr_addr_hi; /* DAM start address for CBR traffic */ freg_t cbr_addr_lo; /* DAM start address for CBR traffic */ freg_t pm_addr_match; /* Packet Memory Address Match register */ uint_t filler3[0x30 - 0x23]; freg_t prq_st_adr; /* Packet Ready Queue Start Address */ freg_t prq_ed_adr; /* Packet Ready Queue End Address */ freg_t prq_rd_ptr; /* Packet Ready Queue read pointer */ freg_t prq_wr_ptr; /* Packet Ready Queue write pointer */ freg_t tcq_st_adr; /* Transmit Complete Queue Start Address*/ freg_t tcq_ed_adr; /* Transmit Complete Queue End Address */ freg_t tcq_rd_ptr; /* Transmit Complete Queue read pointer */ freg_t tcq_wr_ptr; /* Transmit Complete Queue write pointer*/ uint_t filler4[0x40 - 0x38]; freg_t queue_base; /* Base address for PRQ and TCQ */ freg_t desc_base; /* Base address of descriptor table */ freg_t vc_lkup_base; /* Base address for ATM hdr/VC tables */ uint_t filler5[0x45 - 0x43]; freg_t mode_reg_0; /* Mode register 0 */ freg_t mode_reg_1; /* Mode register 1 */ freg_t intr_status_reg; /* Interrupt Status register */ freg_t mask_reg; /* Mask Register */ freg_t cell_ctr_high1; /* Total cell transfer count (high) */ freg_t cell_ctr_lo1; /* Total cell transfer count (low) */ freg_t state_reg; /* Status register */ uint_t filler6[0x50 - 0x4c]; freg_t rq_b0_sdn; /* Band B, rate queue-0 start desc, num */ freg_t rq_b1_sdn; /* Band B, rate queue-1 start desc, num */ freg_t rq_b2_sdn; /* Band B, rate queue-2 start desc, num */ freg_t rq_b3_sdn; /* Band B, rate queue-3 start desc, num */ freg_t rq_a0_sdn; /* Band A, rate queue-0 start desc, num */ freg_t rq_a1_sdn; /* Band A, rate queue-1 start desc, num */ freg_t rq_a2_sdn; /* Band A, rate queue-2 start desc, num */ freg_t rq_a3_sdn; /* Band A, rate queue-3 start desc, num */ freg_t curr_desc_num; /* Contains the current descriptor num */ freg_t cc_label; /* Congestion control VCI */ uint_t filler7[0xc9 - 0x5a]; freg_t cell_ctr_high2; /* Total cell transfer count (high) */ freg_t cell_ctr_lo2; /* Total cell transfer count (low) */ } ffred_t; /* * Atlantic only */ typedef struct _ffredn_t { freg_t idlehead_high; /* Idle cell header (high) */ freg_t idlehead_low; /* Idle cell header (low) */ freg_t maxrate; /* Maximum rate */ freg_t stparms; /* Traffic Management Parameters */ freg_t abrubr_abr; /* ABRUBR Priority Byte 1, TCR Byte 0 */ freg_t rm_type; /* */ uint_t filler5[0x17 - 0x06]; freg_t cmd_reg; /* Command register */ uint_t filler18[0x20 - 0x18]; freg_t cbr_base; /* CBR Pointer Base */ freg_t vbr_base; /* VBR Pointer Base */ freg_t abr_base; /* ABR Pointer Base */ freg_t ubr_base; /* UBR Pointer Base */ uint_t filler24; freg_t vbrwq_base; /* VBR Wait Queue Base */ freg_t abrwq_base; /* ABR Wait Queue Base */ freg_t ubrwq_base; /* UBR Wait Queue Base */ freg_t vct_base; /* Main VC Table Base */ freg_t vcte_base; /* Extended Main VC Table Base */ uint_t filler2a[0x2C - 0x2A]; freg_t cbr_tab_beg; /* CBR Table Begin */ freg_t cbr_tab_end; /* CBR Table End */ freg_t cbr_pointer; /* CBR Pointer */ uint_t filler2f[0x30 - 0x2F]; freg_t prq_st_adr; /* Packet Ready Queue Start Address */ freg_t prq_ed_adr; /* Packet Ready Queue End Address */ freg_t prq_rd_ptr; /* Packet Ready Queue read pointer */ freg_t prq_wr_ptr; /* Packet Ready Queue write pointer */ freg_t tcq_st_adr; /* Transmit Complete Queue Start Address*/ freg_t tcq_ed_adr; /* Transmit Complete Queue End Address */ freg_t tcq_rd_ptr; /* Transmit Complete Queue read pointer */ freg_t tcq_wr_ptr; /* Transmit Complete Queue write pointer*/ uint_t filler38[0x40 - 0x38]; freg_t queue_base; /* Base address for PRQ and TCQ */ freg_t desc_base; /* Base address of descriptor table */ uint_t filler42[0x45 - 0x42]; freg_t mode_reg_0; /* Mode register 0 */ freg_t mode_reg_1; /* Mode register 1 */ freg_t intr_status_reg;/* Interrupt Status register */ freg_t mask_reg; /* Mask Register */ freg_t cell_ctr_high1; /* Total cell transfer count (high) */ freg_t cell_ctr_lo1; /* Total cell transfer count (low) */ freg_t state_reg; /* Status register */ uint_t filler4c[0x58 - 0x4c]; freg_t curr_desc_num; /* Contains the current descriptor num */ freg_t next_desc; /* Next descriptor */ freg_t next_vc; /* Next VC */ uint_t filler5b[0x5d - 0x5b]; freg_t present_slot_cnt;/* Present slot count */ uint_t filler5e[0x6a - 0x5e]; freg_t new_desc_num; /* New descriptor number */ freg_t new_vc; /* New VC */ freg_t sched_tbl_ptr; /* Schedule table pointer */ freg_t vbrwq_wptr; /* VBR wait queue write pointer */ freg_t vbrwq_rptr; /* VBR wait queue read pointer */ freg_t abrwq_wptr; /* ABR wait queue write pointer */ freg_t abrwq_rptr; /* ABR wait queue read pointer */ freg_t ubrwq_wptr; /* UBR wait queue write pointer */ freg_t ubrwq_rptr; /* UBR wait queue read pointer */ freg_t cbr_vc; /* CBR VC */ freg_t vbr_sb_vc; /* VBR SB VC */ freg_t abr_sb_vc; /* ABR SB VC */ freg_t ubr_sb_vc; /* UBR SB VC */ freg_t vbr_next_link; /* VBR next link */ freg_t abr_next_link; /* ABR next link */ freg_t ubr_next_link; /* UBR next link */ uint_t filler7a[0x7c-0x7a]; freg_t out_rate_head; /* Out of rate head */ uint_t filler7d[0xca-0x7d]; /* pad out to full address space */ freg_t cell_ctr_high1_nc;/* Total cell transfer count (high) */ freg_t cell_ctr_lo1_nc;/* Total cell transfer count (low) */ uint_t fillercc[0x100-0xcc]; /* pad out to full address space */ } ffredn_t; /* * Mode Register 0 */ /* Pre-Altantic */ #define F_PM_IF_ASYNC 0x8000 /* Packet mem interface is async */ #define F_PM_IF_WORD 0x4000 /* Packet mem interface is 16 bit */ #define F_PM_PAR_EN 0x2000 /* Enable packet mem parity checking */ #define F_PM_INTRLV 0x1000 /* Packet memory is interleaved */ #define F_PM_REQADR 0x0800 /* See F-FRED doc */ #define F_BNDRY_SYNC 0x0200 #define F_CI_WIDTH16 0x0100 /* Cell interface is 16 bits wide */ #define F_CM_IF_ASYNC 0x0080 /* Control mem interface is async */ #define F_CM_WAIT_EN 0x0040 /* Data transfer subject to CRDY prot */ #define F_CM_PAR_EN 0x0020 /* Enable control mem parity checking */ #define F_CM_ERR_MODE 0x0010 /* Continue on control mem parity err */ #define GNU_MODE 0x0008 #define F_EVEN_PAR 0x0004 /* Control memory is even parity */ /* Common */ #define F_ON_LINE 0x0002 /* Chip is on-line */ #define F_CTRL_WR_DIS 0x0001 /* Controlled regs write-protected */ /* * Mode Register 1 */ /* Common */ #define F_SEND_CBR 0x8000 /* Send SBR data */ #define F_LINK_ONLY_BEG 0x4000 #define F_CBR_XOFF_EN 0x2000 /* CBR traffic is subject to XON/XOFF */ #define F_CM_EARLY_WR 0x1000 /* CWRT pin is pipelined .. early WR */ /* Pre-Atlantic */ #define F_COSET_EN 0x0400 /* Enable hdr cksum XORed with COSET */ #define F_SMDS_CRC32 0x0200 /* IEEE 802.6 CRC appended */ #define F_PARTIAL_CRC8 0x0100 /* Hdr cksum only on cell byte 1-2-3 */ /* Common */ #define F_CONG_DIS 0x0008 /* Disable congestion ctrl mechanism */ #define F_PM_LENDIAN 0x0004 /* Packet memory is Little-endian */ #define F_PM_CRCST_OD 0x0002 /* Packet memory PCYCST* is open drain*/ #define F_CM_CYCST_OD 0x0001 /* Ctrl memory PCYCST* is open drain */ /* * Interrupt Status/Mask register */ /* Pre-Atlantic */ #define F_CM_PARERR 0x8000 /* Control memory parity error */ #define F_NORM_PM_PARERR 0x4000 /* Normal (non-CBR) packet mem error */ #define F_CBR_PM_PARERR 0x2000 /* CBR packet memory error */ /* Common */ #define F_TCQ_NOT_EMPTY 0x1000 /* TCQ went non-empty */ /* Pre-Atlantic */ #define F_TCQ_FULL 0x0800 /* TCQ full */ /* Common */ #define F_TCC_FULL 0x0400 /* Cell counter overflowed */ #define F_TRANSMIT_DONE 0x0200 /* Xmit done (if XD_INTT set in desc) */ /* Pre Atlantic */ #define F_CBR_DONE 0x0100 /* CBR done */ #define F_RQ_A_MIS 0x0080 /* Rate queue in bank A missed service*/ #define F_RQ_B_MIS 0x0040 /* Rate queue in bank B missed service*/ /* * State Register */ /* Common */ #define F_OFF_LINE 0x8000 /* FFRED on line */ /* Pre-Altantic */ #define F_PRQ_FULL 0x4000 /* PRQ full */ /* Common */ #define F_PRQ_EMPTY 0x2000 /* PRQ empty */ #define F_TCQ_EMPTY 0x1000 /* TCQ empty */ /* Pre-Altantic */ #define F_CM_ERROR 0x0800 /* Control memory parity error */ /* * Command register definations */ #define F_SWRESET 0x55 /* Reset ffred */ #define F_SMRESET 0xaa /* Reset ffred state machine */ #define F_TCCRESET 0xcc /* Reset Tx cell counter */ /* * Traffic management parameters * Atlantic only */ #define F_CBR_EN 0x2000 /* Enable CBR */ #define F_VBR_EN 0x1000 /* Enable VBR */ #define F_ABR_EN 0x0800 /* Enable ABR */ #define F_UBR_EN 0x0400 /* Enable UBR */ /* * Rate queue * Pre-Altantic only */ #define RQ_XOFF_EN 0x0800 /* Process rate Q if XON true */ #define RQ_RQ_ENABLE 0x0400 /* Enable rate queue */ #define RQ_PRESCALER_00 0x0000 /* Prescaler = 4 */ #define RQ_PRESCALER_01 0x0100 /* Prescaler = 16 */ #define RQ_PRESCALER_10 0x0200 /* Prescaler = 64 */ #define RQ_PRESCALER_11 0x0300 /* Prescaler = 256 */ #define RQ_PRESCALER_MASK 0x0300 /* Prescaler mask */ #define RQ_PRESCALER_SHIFT 8 struct aal_parms { ushort_t ap_vpci; ushort_t ap_mid; ushort_t ap_orderq; }; typedef struct aal_parms aal_parms_t; /* * ffred buffer descriptor */ typedef struct { ushort_t desc_stat; /* descriptor status bits */ ushort_t vci; /* destination vci */ ushort_t mid; /* mid */ ushort_t length; /* Buf size - packet byte count */ ushort_t buf_high; /* fixed buffer address high */ ushort_t buf_low; /* fixed buffer address low */ ushort_t dma_high; /* dma address high */ ushort_t dma_low; /* dma low address */ /* Pre-Atlantic only */ ushort_t crc_high; /* crc residual high */ ushort_t crc_low; /* crc residual high */ ushort_t nrq; /* NRQ */ ushort_t nvc; /* NVC */ ushort_t que_check; /* 18, used for desc. reconciliation*/ ushort_t buf_index; /* 1a (software) */ ushort_t order_q; /* 1c, used for single threaded vci*/ ushort_t flags; /* 1e, used to idenitify aal */ } f_buf_desc; typedef struct { ushort_t f_desc_ptr; /* bits 1-13 of descriptor address */ } f_desc_q; /* * ffred buffer descriptor status (mode) bits definitions */ #define F_AAL34 0x0000 /* Pre-Atlantic only */ #define F_AAL5 0x0100 #define F_OAM_VC 0x0200 #define F_OAM_DESC 0x0300 #define F_D_APP_CRC32 0x0400 #define F_EOM_EN 0x0800 #define F_XD_INTT_EN 0x1000 #define F_PTI_VALUE_MASK 0xE000 #define F_RAW_CELL_SIZE 52 /* * VC table entry * Pre-Atlantic only */ typedef struct { ushort_t f_prfx01; /* atm prefix 01 */ ushort_t f_prfx23; /* atm prefix 23 */ ushort_t f_hdr01; /* atm header 01 */ ushort_t f_hdr23; /* atm header 23 */ ushort_t f_vcmode; /* vc mode bits */ ushort_t f_avgcc; /* avgcc */ ushort_t f_cq; /* CQ */ ushort_t f_lvc; /* lvc */ } f_vc_table; /* Virtual circuit mode bits */ #define VCM_APP_CR32 0x8000 /* Enable packet CRC */ #define VCM_CC_MODE_1 0x0000 /* Recover after 1 cell */ #define VCM_CC_MODE_2 0x1000 /* Recover after 2 cell */ #define VCM_CC_MODE_4 0x2000 /* Recover after 4 cell */ #define VCM_CC_MODE_8 0x3000 /* Recover after 8 cell */ #define VCM_CC_MODE_16 0x4000 /* Recover after 16 cell */ #define VCM_CC_MODE_SW 0x6000 /* CC set by software */ #define VCM_CC_MODE_FL 0x7000 /* Flush packets on this vc */ #define VCM_RQ_A0 0x0000 /* Bank A, Queue 0 */ #define VCM_RQ_A1 0x0200 /* Bank A, Queue 1 */ #define VCM_RQ_A2 0x0400 /* Bank A, Queue 2 */ #define VCM_RQ_A3 0x0600 /* Bank A, Queue 3 */ #define VCM_RQ_B0 0x0800 /* Bank B, Queue 0 */ #define VCM_RQ_B1 0x0A00 /* Bank B, Queue 1 */ #define VCM_RQ_B2 0x0C00 /* Bank B, Queue 2 */ #define VCM_RQ_B3 0x0E00 /* Bank B, Queue 3 */ #define VCM_RQ_MASK 0x0E00 /* Rate queue mask */ #define VCM_RQ_SHIFT 9 /* Completion codes */ #define F_CC_FLUSH 0x1 /* Descriptor flushed */ #define F_CC_MEMERR 0x7 /* Packet memory error */ /* * VC table entry(s) * Atlantic only */ #define F_VCE_UBR 0xC000 /* UBR */ #define F_VCE_ABR 0x8000 /* ABR */ #define F_VCE_VBR 0x4000 /* VBR */ #define F_VCE_CBR 0x0000 /* CBR */ /* * UBR VC Table Entry */ typedef struct { ushort_t f_vc_type; /* VC type */ ushort_t reserved2[13]; /* Reserved */ ushort_t f_pcr; /* Peak cell rate */ ushort_t f_status; /* Status */ } f_vc_ubr_entry; /* f_status bits (Don't know why this register is called status */ #define F_CRC_APPENDED 0x40 /* * Extended UBR VC Table Entry */ typedef struct { ushort_t f_hdr01; /* atm header 01 */ ushort_t f_hdr23; /* atm header 23 */ ushort_t f_last_desc; /* Last descriptor */ ushort_t reserved6; /* Reserved */ } f_evc_ubr_entry; /* Status bits */ #define VC_UBR_CRC 0x0040 /* CRC appended */ /* * ABR VC Table Entry */ typedef struct { ushort_t f_vc_type; /* VC type */ ushort_t f_nrm; /* Nrm */ ushort_t f_nrmexp; /* Nrm Exp */ ushort_t reserved6; /* */ ushort_t f_crm; /* Crm */ ushort_t reserved10; /* Reserved */ ushort_t reserved12; /* Reserved */ ushort_t reserved14; /* Reserved */ ushort_t last_cell_slot; /* last_cell_slot_count */ ushort_t f_pcr; /* Peak Cell Rate */ ushort_t fraction; /* fraction */ ushort_t f_icr; /* Initial Cell Rate */ ushort_t f_cdf; /* */ ushort_t f_mcr; /* Minimum Cell Rate */ ushort_t f_acr; /* Allowed Cell Rate */ ushort_t f_status; /* */ } f_vc_abr_entry; /* f_status bits #define F_UIOLI 0x80 #define F_OOR_RM 0x20 #define F_RM_PRESENT 0x10 #define F_FWD_REDUCE 0x08 #define F_ABR_STATE 0x07 /* Mask */ /* * Extended ABR VC Table Entry */ typedef struct { ushort_t f_hdr01; /* atm header 01 */ ushort_t f_hdr23; /* atm header 23 */ ushort_t f_last_desc; /* Last descriptor */ ushort_t reserved6; /* Reserved */ } f_evc_abr_entry; /* Status bits */ #define VC_ABR_CRC 0x0040 /* CRC appended */ /******************************** R-Fred ********************************/ typedef uint_t rreg_t; /* * Pre-Atlantic only */ typedef struct _rfred_t { rreg_t mode_reg_0; /* Mode register 0 */ rreg_t mode_reg_1; /* Mode register 1 */ rreg_t mask_reg; /* Mask Register */ rreg_t intr_status_reg; /* Interrupt status register */ rreg_t drp_pkt_cntr; /* Dropped packet cntr (clear on read) */ rreg_t err_cntr; /* Error Counter (cleared on read) */ rreg_t drp_cbr_cntr; /* Dropped CBR cells (cleared on read) */ uint_t filler1[0x08 - 0x07]; rreg_t cbr_base_adr; /* Base addr for CBR/congestion cntrl Q */ rreg_t pm_addr_match; /* Packet memory address match register */ uint_t filler2[0x0c - 0x0a]; rreg_t cell_ctr0; /* Cell Counter 0 (cleared when read) */ rreg_t cell_ctr1; /* Cell Counter 1 (cleared when read) */ uint_t filler3[0x0f - 0x0e]; rreg_t cmd_reg; /* Command register */ rreg_t desc_base; /* Base address for description table */ rreg_t vc_lkup_base; /* Base address for VC lookup table */ rreg_t reass_base; /* Base address for reassembler table */ rreg_t queue_base; /* Base address for Communication queue */ uint_t filler4[0x16 - 0x14]; rreg_t pkt_tm_cnt; /* Packet Timeout and count register */ rreg_t tmout_range; /* Range of reassembley IDs for timeout */ rreg_t intrvl_cntr; /* Packet aging interval counter */ rreg_t tmout_indx; /* index of pkt being tested for aging */ uint_t filler5[0x1c - 0x1a]; rreg_t vp_lkup_base; /* Base address for VP lookup table */ rreg_t vp_filter; /* VP filter register */ uint_t filler6[0x20 - 0x1e]; rreg_t sml_st_adr; /* Small Free desc queue start address */ rreg_t sml_ed_adr; /* Small Free desc queue end address */ rreg_t sml_rd_ptr; /* Small Free desc queue read pointer */ rreg_t sml_wr_ptr; /* Small Free desc queue write pointer */ rreg_t lrg_st_adr; /* Large Free desc queue start address */ rreg_t lrg_ed_adr; /* Large Free desc queue end address */ rreg_t lrg_rd_ptr; /* Large Free desc queue read pointer */ rreg_t lrg_wr_ptr; /* Large Free desc queue write pointer */ rreg_t pcq_st_adr; /* Packet Complete queue start address */ rreg_t pcq_ed_adr; /* Packet Complete queue end address */ rreg_t pcq_rd_ptr; /* Packet Complete queue read pointer */ rreg_t pcq_wr_ptr; /* Packet Complete queue write pointer */ rreg_t excp_st_adr; /* Exception queue start address */ rreg_t excp_ed_adr; /* Exception queue end address */ rreg_t excp_rd_ptr; /* Exception queue read pointer */ rreg_t excp_wr_ptr; /* Exception queue write pointer */ rreg_t cbr_st_adr; /* CBR queue start address */ rreg_t cbr_ed_adr; /* CBR queue end address */ rreg_t cbr_rd_ptr; /* CBR queue read pointer */ rreg_t cbr_wr_ptr; /* CBR queue write pointer */ rreg_t raw_st_adr; /* Raw Cell start address */ rreg_t raw_ed_adr; /* Raw Cell end address */ rreg_t raw_rd_ptr; /* Raw Cell read pointer */ rreg_t raw_wr_ptr; /* Raw Cell write pointer */ rreg_t state_reg; /* State Register */ uint_t filler7[0x40 - 0x39]; rreg_t sml_buf_chk; /* BA-size compare reg for small buffers*/ rreg_t lrg_buf_chk; /* BA-size compare reg for large buffers*/ rreg_t lrg_buf_size; /* Large Buffer size */ uint_t filler8[0x44 - 0x43]; rreg_t qamcc_chk; /* OAM F5 code - congestion cntrl cells */ uint_t filler9[0x84 - 0x45]; rreg_t drp_pkt_cntr_nc; /* Dropped Packet cntr, Not clear on rd */ rreg_t err_cntr_nc; /* Error Counter, Not clear on read */ rreg_t drp_cbr_cntr_nc; /* Dropped CBR cells cntr, Not clear */ uint_t filler10[0x8c - 0x87]; rreg_t cell_ctr0_nc; /* Cell Counter 0, Not clear on read */ rreg_t cell_ctr1_nc; /* Cell Counter 1, Not clear on read */ uint_t filler11[0x100 - 0x8e]; /* pad out to full address space */ } rfred_t; /* * Atlantic only */ typedef struct _rfredn_t { rreg_t mode_reg_0; /* Mode register 0 */ rreg_t protocol_id; /* Protocol ID */ rreg_t mask_reg; /* Mask Register */ rreg_t intr_status_reg;/* Interrupt status register */ rreg_t drp_pkt_cntr; /* Dropped packet cntr (clear on read) */ rreg_t err_cntr; /* Error Counter (cleared on read) */ uint_t filler6[0x08 - 0x06]; rreg_t raw_base_adr; /* Base addr for raw cell Q */ uint_t filler2[0x0c - 0x09]; rreg_t cell_ctr0; /* Cell Counter 0 (cleared when read) */ rreg_t cell_ctr1; /* Cell Counter 1 (cleared when read) */ uint_t filler3[0x0f - 0x0e]; rreg_t cmd_reg; /* Command register */ rreg_t desc_base; /* Base address for description table */ rreg_t vc_lkup_base; /* Base address for VC lookup table */ rreg_t reass_base; /* Base address for reassembler table */ rreg_t queue_base; /* Base address for Communication queue */ uint_t filler14[0x16 - 0x14]; rreg_t pkt_tm_cnt; /* Packet Timeout and count register */ rreg_t tmout_range; /* Range of reassembley IDs for timeout */ rreg_t intrvl_cntr; /* Packet aging interval counter */ rreg_t tmout_indx; /* index of pkt being tested for aging */ uint_t filler1a[0x1c - 0x1a]; rreg_t vp_lkup_base; /* Base address for VP lookup table */ rreg_t vp_filter; /* VP filter register */ rreg_t abr_lkup_base; /* Base address of ABR VC Table */ uint_t filler1f[0x24 - 0x1f]; rreg_t fdq_st_adr; /* Free desc queue start address */ rreg_t fdq_ed_adr; /* Free desc queue end address */ rreg_t fdq_rd_ptr; /* Free desc queue read pointer */ rreg_t fdq_wr_ptr; /* Free desc queue write pointer */ rreg_t pcq_st_adr; /* Packet Complete queue start address */ rreg_t pcq_ed_adr; /* Packet Complete queue end address */ rreg_t pcq_rd_ptr; /* Packet Complete queue read pointer */ rreg_t pcq_wr_ptr; /* Packet Complete queue write pointer */ rreg_t excp_st_adr; /* Exception queue start address */ rreg_t excp_ed_adr; /* Exception queue end address */ rreg_t excp_rd_ptr; /* Exception queue read pointer */ rreg_t excp_wr_ptr; /* Exception queue write pointer */ uint_t filler30[0x34 - 0x30]; rreg_t raw_st_adr; /* Raw Cell start address */ rreg_t raw_ed_adr; /* Raw Cell end address */ rreg_t raw_rd_ptr; /* Raw Cell read pointer */ rreg_t raw_wr_ptr; /* Raw Cell write pointer */ rreg_t state_reg; /* State Register */ uint_t filler39[0x42 - 0x39]; rreg_t buf_size; /* Buffer size */ uint_t filler43; rreg_t xtra_rm_offset; /* Offset of the additional turnaround RM */ uint_t filler45[0x84 - 0x45]; rreg_t drp_pkt_cntr_nc;/* Dropped Packet cntr, Not clear on rd */ rreg_t err_cntr_nc; /* Error Counter, Not clear on read */ uint_t filler86[0x8c - 0x86]; rreg_t cell_ctr0_nc; /* Cell Counter 0, Not clear on read */ rreg_t cell_ctr1_nc; /* Cell Counter 1, Not clear on read */ uint_t filler8e[0x100-0x8e]; /* pad out to full address space */ } rfredn_t; /* * Mode Register 0 */ /* Pre-Atlantic only */ #define R_CM_EARLY_WR 0x8000 #define R_CM_PAR_EN 0x4000 #define R_CM_WAIT_EN 0x2000 #define R_CM_IF_ASYNC 0x1000 #define R_PM_REQADR 0x0800 #define R_PM_DATADLY 0x0400 #define R_PM_IF_ASYNC 0x0200 #define R_PM_IF_WORD 0x0100 #define R_CI_BNDRY_CHK 0x0080 #define R_CI_PAR_EN 0x0040 #define R_CI_WIDTH16 0x0020 /* Atlantic only */ #define R_NO_PROT_ID_CHECK 0x0040 #define R_NO_CRC_CHECK 0x0020 #define R_RM_TRANSFER_ENABLE 0x0010 /* Pre-Atlantic only */ #define R_IGN_CBR_FL 0x0008 /* Common */ #define R_IGN_RAW_FL 0x0004 #define R_ON_LINE 0x0002 /* Pre-Atlantic only */ #define R_CTRL_WR_DIS 0x0001 /* * Mode Register 1 */ /* Pre-Atlantic only. (All bits) */ #define R_PM_CYCST_ACT 0x0800 #define R_CM_CYCST_ACT 0x0400 #define R_CC_GFC_EN 0x0200 #define R_CC_OAMF5_EN 0x0100 #define R_SMDS_CRC32 0x0080 #define R_COSET_EN 0x0040 #define R_PARTIAL_CRC8 0x0020 #define R_PM_LENDIAN 0x0010 #define R_PM_INTRLV 0x0008 #define R_CC_CRC10 0x0004 #define R_CC_XFER_EN 0x0002 #define R_EVEN_PARITY 0x0001 /* * Interrupt Status/Mask Register */ /* Pre-Atlantic */ #define R_CBR_CTR_OF 0x2000 /* Sync counter overflow */ #define R_CM_PARERR 0x0400 /* Control memory parity error */ #define R_LRG_FREEQ_MT 0x0200 /* No Large free descriptor */ #define R_SML_FREEQ_MT 0x0100 /* No Small free descriptor */ #define R_PCQ_FL_I 0x0040 /* Complete queue full */ #define R_CBRQ_FL_I 0x0020 /* Sync fifo full */ #define R_CBR_RCVD 0x0002 /* Sync cell received */ /* Common */ #define R_PKT_CTR_OF 0x8000 /* Drop packet counter overflow */ #define R_ERR_CTR_OF 0x4000 /* Error cell counter overflow */ #define R_CELL_CTR_OF 0x1000 /* Received cell counter o-flow */ #define R_FREEQ_MT 0x0200 /* No free descriptor */ #define R_EXCPQ_FL_I 0x0080 /* Exception queue full */ #define R_RAWQ_FL_I 0x0010 /* Flow control fifo full */ #define R_EXCP_RCVD 0x0008 /* Excepton error occurred */ #define R_PKT_RCVD 0x0004 /* Packet received */ #define R_RAW_RCVD 0x0001 /* Flow control cell received */ /* * State Register */ /* Pre-Atlantic */ #define R_CBRQ_FULL 0x0200 /* Sync fifo full */ #define R_CBRQ_EMPTY 0x0100 /* Sync fifo empty */ #define R_PCQ_FULL 0x0020 /* packet complete queue full */ #define R_PCQ_EMPTY 0x0010 /* packet complete queue empty */ #define R_LRGQ_FULL 0x0008 /* Large descriptor queue full */ #define R_LRGQ_EMPTY 0x0004 /* Large descriptor queue empty */ #define R_SMLQ_FULL 0x0002 /* Small descriptor queue full */ #define R_SMLQ_EMPTY 0x0001 /* Small descriptor queue empty */ /* Common */ #define R_OFF_LINE 0x8000 /* Main state machine state */ #define R_RAWQ_FULL 0x0800 /* Flow control fifo full */ #define R_RAWQ_EMPTY 0x0400 /* Flow control fifo empty */ #define R_EXCPQ_FULL 0x0080 /* Exception queue full */ #define R_EXCPQ_EMPTY 0x0040 /* Exception queue empty */ #define R_PCQ_EMPTY 0x0010 /* Packet complete queue empty */ #define R_Q_EMPTY 0x0004 /* Descriptor queue empty */ /* * Command register definitions */ #define R_SWRESET 0x0055 /* Reset the entire chip */ #define R_SMRESET 0x00aa /* Reset just the State Machine */ #define R_CLR_PKTCTR 0x00f1 /* Reset the dropped Packet Counter */ #define R_CLR_ERRCTR 0x00f2 /* Reset the Error cell Counter */ #define R_CLR_SYNCCTR 0x00f4 /* Reset the dropped Sync cell Cnter */ #define R_CLR_CELLCTR 0x00f8 /* Reset the Cell Counters */ /* * rfred buffer descriptor * Use the same structure as for ffred buffer descriptor */ #define r_buf_desc f_buf_desc #define pkt_timeout nrq /* Pre-Atlantic only */ /* * Buffer descriptor status bits */ /* Common */ #define R_ACT 0x8000 /* Reassembly active */ #define R_VP_VC 0x4000 /* VPI/VCI reassembly */ /* Pre-Altantic only */ #define R_LARGE 0x1000 /* Large size buffer */ /* * Buffer descriptor errors */ /* Pre-Atlantic only */ #define R_PKT_ERROR 0x003f /* Mask for any packet error */ #define R_EOF 0x0020 /* End of frame error */ #define R_CF 0x0020 /* Cell flushed error */ #define R_PEP 0x0010 /* Payload error */ #define R_CCE 0x0008 /* Cell crc error */ #define R_CSE 0x0004 /* Cell size error */ #define R_SQE 0x0002 /* Sequence error */ #define R_CPE 0x0001 /* Cell error */ #define R_RSE 0x0080 /* Roll-over sequence error */ #define R_BADDESC 0x00C0 /* Bad descriptor status */ /* Common */ #define R_CNG 0x0040 /* Congestion experienced */ #define R_CER 0x0008 /* Packet crc error */ #define R_PTE 0x0004 /* Packet timeout error */ #define R_OFL 0x0002 /* Buffer overflow error */ /* * Exception queue entity */ typedef struct { ushort_t vc_label; /* Virtual circuit index */ ushort_t error; /* Error code */ } R_ERROR_Q; /* * Exception queue errors */ /* Common */ #define R_EXCPT_MASK 0x07 /* Error bits mask */ /* Pre-Atlantic only */ #define R_OOS_COM 0x01 /* Out of sequence COM */ #define R_OOS_EOM 0x02 /* Out of sequence EOM */ #define R_NFD 0x03 /* No free descriptor */ #define R_NSLD 0x04 /* No free Small/Large desc */ /* Common */ #define R_NLD 0x05 /* No free Large descriptor */ #define R_INVLDVC 0x06 /* Cell received on invalid VC */ #define R_INVLDVP 0x07 /* Cell received on invalid VP */ /* * Reassembly table status bits */ /* Pre-Atlantic */ #define AAL3PKT_NOT_ACTIVE 0x0000 /* no AAL34 packet active */ #define AAL3PKT_ASSEMBLE 0x4000 /* AAL34 packet being assembled */ #define AAL3PKT_TERMINATED 0x8000 /* AAL34 packet terminated */ #define AAL5PKT_NOT_ACTIVE 0x2000 /* no AAL5 packet active */ #define AAL5PKT_ASSEMBLE 0x6000 /* AAL5 packet being assembled */ #define AAL5PKT_TERMINATED 0xa000 /* AAL3 packet terminated */ #define CBR_TRAFFIC 0xc000 /* CBR traffic */ #define RAW_CELL_TRAFFIC 0xe000 /* Raw cell traffic */ #define AALTYP_3 0x0000 /* AAL type is 3/4 */ #define AALTYP_5 0x2000 /* AAL type is 5 */ /* Atlantic only */ #define AAL5PKT_NOT_ACTIVE_N 0x0000 /* no AAL5 packet active */ #define ABR_VC_N 0x2000 /* ABR VCa */ #define AAL5PKT_ASSEMBLE_N 0x4000 /* AAL5 packet being assembled */ #define AAL5PKT_TERMINATED_N 0x8000 /* AAL3 packet terminated */ #define RAW_CELL_TRAFFIC_N 0xc000 /* Raw cell traffic */ /* * ABR VC Table Entry */ typedef struct { ushort_t r_status_rdf; /* status + RDF */ ushort_t r_air; /* AIR */ ushort_t reserved4[14]; /* Reserved */ } r_vc_abr_entry; #endif /* _FRED_H */