From: Jesper Vasell N[r jag var p} SPDP90 (Symp. on Parallel and Distributed Processing) i December s} tr{ffade jag en australiensare som hade utvecklat n}gonting }t det h}llet. Hans namn och adress {r: A.N. Pears La Trobe University Bundoora 3083 Australia ---------------------------------------------------------------------- From: " (Roland Ruehl)" @inproceedings{K9, author = "P. Beadle and C. Pommerell and M. Annaratone", title = "{K9}: A simulator of distributed-memory parallel processors", booktitle = "Proc. Supercomputing 89", address = "Reno, Nevada", organization = "ACM-IEEE", page = "765-774", month = "November", year = "1989"} ---------------------------------------------------------------------- From: Marc Brandis K9 Simulator Integrated Systems Laboratory ETH-Zentrum, ETZ Building CH-8092 Zurich Prof. Marco Annaratone, email mxa@iis.ethz.ch Claude Pommerell, email pommy@iis.ethz.ch From: tyang@paul.rutgers.edu ---------------------------------------------------------------------- T.H. Dunigan group at Roak Ridge National Laboratory, TN 37831 has developed one or two simulator(s) for message-passing architecture (e.g. iPSC) in 1986. ---------------------------------------------------------------------- From: tiff@CS.UCLA.EDU (Tiffany Frazier) Many of us at UCLA are using SIMON - which is exactly what you describe. Univ. of Utah - Fujimoto ---------------------------------------------------------------------- From: Jean-yves Colin In 1989, A.Joubert in France, built such a simulator, called SiGLe. It was his PhD subject and the result was really interesting. You could try to contact his co-author, F.Andre at 'andre@irisa.fr' (if she still works there !). ---------------------------------------------------------------------- From: John.Willis@CS.CMU.EDU Auriga is an experimental optimizing compiler translating VHDL models (such as a multiprocessor) into a parallel simulation running on a network of message-passing nodes. ---------------------------------------------------------------------- From: petter@idt.unit.no Jeg brukte et halvt aar paa aa simulere oppfoerselen av programmer skrevet i POOL, eksekvert paa POOMA-maskinen, (for en introduksjon til begge se proceedings, PARLE 1989). Jeg har et paper om det som jeg kan sende deg dersom det er av interesse, men dette er forholdsvis hoeynivaa simulering, og overser detaljer som registerbruk, "peephole"-optimaliseringer etc. Petter Moe Department of Computer Systems and Telematics The Norwegian Institute of Technology phone: +47-7-593470 N-7034 TRONDHEIM - NTH fax: +47-7-594466 NORWAY e-mail: petter@idt.unit.no ---------------------------------------------------------------------- From: ronald@ixstar.att.com (Ronald H Davis) Jeffrey T. Kreulen and Matthew J. Thazhuthaveetil. "Application-dependent Simulation of Microprocessor-based Multiprocessors" Microprocessors and Microsystems. september 1990. the authorsy are affiliated with pennsylvania state university (usa) ---------------------------------------------------------------------- From: Miltos Dimitris Grammatikakis 1) L. G. Valiant, " Experiments with a parallel communication scheme ", Proceedings of the 18th Allerton Conference on Communication, Control and Computing, University of Illinois, October 1980, pp. 802-811. 2) L. Kleinrock, Communication Networks, Mc Graw Hill 1964. 3) M. Grammatikakis, S. Lakshmivarahan, and S. K. Dhall, "Experiments on Probabilistic Routing for a Generalized Hypercube ", Proceedings of the Workshop on Applied Computing 1989, pp. 131-133. 4) M. Grammatikakis, S. Lakshmivarahan, and S. K. Dhall, "Packet Routing for Generalized Hypercube ", Proceedings of the 24th Annual Conference on Computer, Information and Communication Systems, Princeton, NJ, March 1990, pp. 159-164. 5) M. Grammatikakis, "Probabilistic Routing Algorithms for Generalized Hypercube", Proceedings of the 25th Annual Conference on Computer, Information and Communication Systems, Baltimore, MD, March 1991 ( submitted ). 6) D. Nassimi and S. Sahni, " Optimal BPC Permutations on a Cube Connected SIMD Computer ", IEEE Transactions on Computers, C-31 (4), April 1982 pp. 338-341. As a last note let me say that I am simulating the star network and connection machine. If you need a copy of 3,4,5, above let me know. ---------------------------------------------------------------------- From: haines@debussy.cs.colostate.edu (Matt Haines) I know that there is an NCube simulator that runs on Sun's, but that's about all. ---------------------------------------------------------------------- From: Claude.Jard@irisa.fr (Claude Jard) I am working on simulation, and that for several years. We have designed different kinds of simulator, all based on the Estelle description language. The Estelle model (now an ISO standard for describing protocols) is very closed to the model of Distributed Memory Parallel Computers like iPSC if you look at the system level. Maybe too abstract for your purpose but solves some problems for developing distributed programs. References: C. Jard, R. Groz, JF. Monin, Development of Veda: a Prototyping Tool for Distributed Algorithms, IEEE tr. on SE, Vol14, no3, March 88. C. Jard, JM, Jezequel, A Multiprocessor Estelle to C Compiler to prototype Distributed Algorithms on Parallel Machines, proc. of the 9th IFIP int. symposium on Protocol Specification, Testing and Verification, Twente univ., The Netherlands, North-Holland, June 89. ---------------------------------------------------------------------- From: u502sou@mpirbn.mpifr-bonn.mpg.de (Ignatios Souvatzis) Contact Tom Dunigan at Oak Ridge National Laboratory (US of A), . He has an IPS/2 simulator for a single or a net of homogenous workstations of BSD Unix systems. ---------------------------------------------------------------------- From: O A El-Ghajiji I am working on a parallel computer simulator as a part of my Ph. d. research. It will simulate a dataflow multiprocessor computer. The objectives of the simulator is to obtain an approximate execution times for a number of different algorithms by varying some hardware parameters. Mr Otman A. El-Ghajiji School of electrical engineering University of Bath, Claverton Down, Bath Avon United Kingdom. eepoaeg@uk.ac.bath.gdr ---------------------------------------------------------------------- From: agn@Eng.Sun.COM (Andreas G. Nowatzyk) I wrote several of those. Two of them are described in my PhD thesis, "A Communication Architecture for Multiprocessor Networks", CMU-CS-89-181, School of Computer Science, Carnegie Mellon University, Pittsburgh PA 15213-3890, USA ---------------------------------------------------------------------- From: harrison@tcg.anl.gov You may be interested in a set of tools (TCGMSG) that we have developed and been using for the last year. TCGMSG is aimed at scientific applications in FORTRAN or C and strives to provide a robust, portable and efficient message passing environment. Robert J. Harrison tel: (708) 972-7197 E-mail: harrison@tcg.anl.gov, harrison@anlchm.bitnet letter: Bldg. 200, Theoretical Chemistry Group, Argonne National Laboratory, 9700 S. Cass Avenue, Argonne, IL 60439. ---------------------------------------------------------------------- From: upchurch@hyper-gemini.Jpl.Nasa.Gov (Ed Upchurch) I have done a considerable amount of modeling and simulating distributed memory architectures particularily hypercubes built here at CalTech and JPL. I have detailed models of the Mark III and of the next generation of our own adaptive routing/fault tolerant hypercube architecture. The models use SES/workbench an easy to use graphical modeling language. Dr Ed Upchurch Jet Propulsion Lab CalTech 4800 Oak Grove Drive Pasadena, California 91109 (818) 354-8731 upchurch@hyper-gemini.Jpl.Nasa.Gov ---------------------------------------------------------------------- From: Roldan Pozo We have a generic simulator that runs on any Unix box. The simulator was developed by Oliver McBryan, the director of the Center for Applied Parallel Processing, and handles iPSC/1, iSPC/2, iPSC/860, and Caltech message primitives. *********** ***** ***** Roldan Pozo ***** ***** Center for Applied Parallel Processing ***** ***** and Department of Computer Science ***** ***** University of Colorado ***** ***** Boulder, CO 80309-430 ***** ***** ***** ***** Email: roldan@boulder.colorado.EDU ***** ***** Phone: (303) 492-7514 ---------------------------------------------------------------------- From: cfleck@src.honeywell.com (Chuck Fleckentein) You should talk to Bill Bain (Intel). He wrote the original simulator for the iPSC/2. He has his own company also: Block Island Technologies 15455 NW Greenbrier Parkway Suite 210 Beaverton, Oregon 97006 (503) 690-7181 I believe his email address is wlb@isc.intel.com ---------------------------------------------------------------------- From: kitajima@alize.imag.fr (Joao Paulo Kitajima) "This document describes the implementation and use of a self-driven discrete event simulation model of a restricted class of MIMD (Multiple Instruction stream Multiple Data stream) machine and a distributed communicating sequential process program..." The tool is very flexible because you can simulate not only hypercubes, but any loosely-coupled architecture. Here goes the pointer: Skilling, Neil Department of Chemical Engineering The King's Buildings University of Edinburgh Mayfield Road - Edinburgh - EH9 1HA e-mail: neil@uk.ac.ed.chemeng (I think that for UK you have to change this order,i.e., neil@chemeng.ed.ac.uk) tel: 031-650 4867 ---------------------------------------------------------------------- From: loran@Eng.Sun.COM (Loran Ball) Our simulator is written entirely in C and runs under Unix. It simulates a set of modules that pass messages back and forth. Modules can be anything but currently we have modules that together simulate some of our systems. Some of the modules we have are: SPARC processor SPARC floating point unit RAM ROM various MMU's various buses (ex. Mbus, Sbus) various I/O devices (serial, disk, etc) loran@Eng.Sun.COM (Loran Ball) ---------------------------------------------------------------------- From: watro@linus.mitre.org "Modeling Internode Communication For Hypercube Architectures" by Upchurch and Neuse (SCS Summer Sim Conf, July 89). This paper is based on communication in the JPL Mark III hypercube. >From noose.ecn.purdue.edu!samsung!zaphod.mps.ohio-state.edu!wuarchive!emory!hubcap!Tom Mon Mar 11 10:41:37 EST 1991 Add to the list of distributed simulators my simulator of an MIMD shared memory design (called EPP1) on a transputer network. I simulated up to a 256 processor system on 128 transputers, and the simulator is written in Occam. The simulator is specific to this design though the same simulation methodology (parallel time-driven) is applicable to other simulations. A paper on simulator may appear in a special issue of the International Journal of Computer Simulation (this is uncomfirmed). Some of the results are presented in a technical report: "Combining in an MIMD shared memory multiprocessor simulation", EPCC-TR-90-09. Available from the Edinburgh Parallel Computing Centre, University of Edinburgh, JCMB, Kings Buildings, Mayfield Road, Edinburgh EH9 3JZ. UK. Thankyou for your attention. Tom. >From noose.ecn.purdue.edu!samsung!uunet!bonnie.concordia.ca!thunder.mcrcim.mcgill.edu!govindr Fri Jan 10 10:48:43 EST 1992 Hi! In the first place, thanks to everyone who responded to my earlier posting in the net! In particular thanks to the following who provided information on the parallel architecture simulators available by anonymous ftp. > Nan C Schaller (ncs@cs.rit.edu) > David Kotz (dfk@wildcat.dartmouth.edu) > Jihong Kim (jihong@cs.washington.edu ) > Walt Ligon (walt@cc.gatech.edu) > Jaswinder Pal Singh (jps@samay.stanford.edu) > Stefan Engelhardt (Engelhardt@informatik.uni-stuttgart.dbp.de) > Marshall Brain (brain@eos.ncsu.edu) > Jim Burrill (burrill@aai.com) > Hemant Rotithor (hemant@wpi.WPI.EDU) > George Wilson (gwilson@umiacs.UMD.EDU) > Zhongyun Zhang (zz@cs.princeton.edu) > Stephen Goldschmidt (comments@meadow.stanford.edu) Lastly, I received at least 10 requests to post a summary in the net. So here it is: Thanks again to every one, Govind =-----------------------------------------------------------= Govindarajan Ramaswamy Ph: (514) 398 8169 (O) VLSI Design Laboratory (514) 287 8964 (H) Electrical Engineering McGill University Fax: (514) 398 4470 3480 University Street MONTREAL, H3A 2A7, Canada govindr@pike.ee.mcgill.ca =-----------------------------------------------------------= ___________________________________________________________________ THE P A R A L L A X I S MASSIVELY PARALLEL PROGRAMMING SYSTEM ___________________________________________________________________ ----------------------------------- Announcing Parallaxis Version 2.0 ----------------------------------- Parallaxis is a procedural programming language based on Modula-2, but extended for data parallel (SIMD) programming. It has been developed at the Universitaet Stuttgart (Germany) and is in the public domain since 1990. The main approach for machine independent parallel programming is to include a description of the virtual parallel machine with each parallel algorithm. The declaration includes the number of identical processors with local memory (PEs), the names of communication ports, and the network topology for data exchange among PEs. With this information contained in each program, the parallel algorithm becomes simpler (e.g. symbolic names for communication directions) and easier to understand. In Version 2 we extended the language in several ways: o multiple configuration and connection structures allow semi-dynamic topologies o new data exchange operations for exchanging data with inactive PEs and with implicit reductions allow general m:n connections o data structures pointer and variant record have been added The simulation system has also been extended: o compiler optionally generates cross-reference files for the o symbolic debugger on Parallaxis source level The Parallaxis system comprises a compiler and a simulator (except forthe MasPar , which is the only parallel implementation as of today). The versions currently available are: * IBM-PC (DOS) * Apple Macintosh (MAC OS) * Sun3 w/ coproc. (OS 4.0) * Sun3 w/o coproc. (OS 4.0) * SPARCstation / Sun4 (OS 4.0) * DECstation (Ultrix) * VAXstation (Ultrix) * HP 9000/300 (Unix) * HP /800 series (Unix) * Cray-2 (scalar only, sorry) * Apollo (available soon) * MasPar MP-1 (available July 1991) The software packages and a number of example programs are available via "anonymous ftp" from: ftp.informatik.uni-stuttgart.de (129.69.211.1) in subdirectory pub/parallaxis Please send remarks and bug reports to: braunl@informatik.uni-stuttgart.de There is also a new User Manual for Parallaxis Version 2.0 . You may order a copy by sending a fee (cash or cheque) of DM 10.00 (Europe) or US$ 15.00 (outside Europe) to: Thomas Braunl, Univ. Stuttgart IPVR Breitwiesenstr. 20-22, D-7000 Stuttgart 80 Germany FAX: +49 (711) 7816-346 ========================================================================== Thomas Braunl e-mail: braunl@informatik.uni-stuttgart.de Univ. Stuttgart IPVR, Breitwiesenstr. 20-22, D-7000 Stuttgart 80, Germany ========================================================================== HINTS FOR VERSION 2 The power operator is now "**". It is now possible to define multiple topologies at once (disjunct or overlay), or different topologies for procedures that are not nested. If multiple topologies are used, the topology name has to be specified for each PARALLEL block. Since connections are now semi-dynamic, there are no lengthy connection lists any more at the beginning of each PARZ intermediate code program. The simulator has been extended to operate source level debugging. For this reason, the compiler optionally generates a cross reference file (".xrf"). LITERATURE in English: Barth, Braunl, Sembach: Parallaxis Version 2 User Manual Computer Science Report, no. 2/91, Universitaet Stuttgart, Feb. 1991 --> This report is a must for using Parallaxis !! <-- --> Contact the address below. <-- Barth, Braunl, Sembach: Parallaxis User Manual Computer Science Report, no. 3/90, Universitaet Stuttgart, March 1990 Braunl: Parallaxis: A Flexible Parallel Programming Environment for AI Applications, Applications of Artificial Intelligence VII, Orlando Florida, March 1989, pp. 275 (11) Braunl: A Specification Language for Parallel Architectures and Algorithms, Fifth International Workshop on Software Specification and Design, Pittsburgh Pennsylvania, May 1989, pp. 49 (3) Braunl: Structured SIMD Programming in Parallaxis, Structured Programming, vol. 10, no. 3, July 1989, pp. 121 (12) Braunl: Transparent Massively Parallel Programming with Parallaxis, ISSM International Conference on Parallel and Distributed Computing and Systems, New York NY, Oct. 1990 in German: Barth: Entwicklung eines Compilers fuer die parallele Programmiersprache Parallaxis, Studienarbeit Nr. 835, Universitaet Stuttgart, March 1990 Barth: Entwicklung eines Compilers fuer Parallaxis mit dynamischen Verbindungsstrukturen, Diplomarbeit Nr. 705, Universitaet Stuttgart, Nov. 1990 Braunl: Massiv parallele Programmierung mit dem Parallaxis-Modell Informatik-Fachberichte Nr. 246, Springer-Verlag 1990. Krauskopf: Ein massiv paralleles Verfahren zur Stereobildauswertung, Diplomarbeit, Universitaet Stuttgart Nr. 707, Nov. 1990 Liebelt: Entwicklung und Untersuchung von massiv parallelen Hidden-Surface- und Raytracing-Algorithmen, Diplomarbeit Nr. 769, Universitaet Stuttgart, Jan. 1991 Sembach: Entwicklung eines Simulators fuer die parallele Zwischensprache PARZ, Studienarbeit Nr. 834, Universitaet Stuttgart, March 1990 Sembach: Entwicklung eines symbolischen Debuggers fuer das parallele Sprachensystem Parallaxis/PARZ, Diplomarbeit Nr. 706, Universitaet Stuttgart, Nov. 1990 Verba: Massiv-parallele Algorithmen zur Loesung von Problemen der linearen Algebra, Studienarbeit Nr. 904, Universitaet Stuttgart, Nov. 1990 Walter: Entwurf von massiv parallelen Simulated Annealing Algorithmen, Studienarbeit Nr. 925, Universitaet Stuttgart, Jan. 1991 ^L What's New in Version Two ========================= In version 2 of the Parallaxis language definition and the Parallaxis Programming System we did some major extensions, the most important being the introduction of semi-dynamical connection structures. Parallaxis programs may now have several independent or overlapping interconnection structures at a time, and different connection structures at different times (linked to procedure scopes). We tried to be upward compatible as much as possible, however, there are two minor changes you might have to do in order to run your old (version 1) Parallaxis programs: How to upgrade old Parallaxis Programs * change power operator symbol from "^" to "**" * suffix load/store commands in procedures without selection with "[*]" selection Language Changes Data Types and Operators * Pointers * Variant Records * power operator "**" Dynamic data structures and variant record structures have been added. Syntax and Semantics is identical to Modula-2. The power operator had to be changed to double asterik, since the "^" symbol is now used for dereferencing pointer expressions. Multiple Configuration and Connection Structures Several configuation and connection structures may be defined globally for the entire program, or locally for each procedure. Procedures with configuration/ connection structures may not be nested inside each other. Multiple configuration/connection structures may be defined on disjointed sets of PEs (with the possibility of interconnections between these groups), each having its individual data declaration. Several configuration/connection structures may also be defined on the same set of PEs, resulting in an overlay structure. PE selection syntax in PARALLEL, LOAD/STORE, and REDUCE statements has been changed slightly because of this extension. Besides the PE-range, a selection also has to specify the name of the configuration in case there are more than one (massively parallel MasPar computer system (16,384 PEs). We hope to be able to start distribution soon! REGISTRATION / ORDER SHEET FOR THE PARALLAXIS SOFTWARE PACKAGE Please fill in the blanks and return to: Dr. Thomas Braunl Universitaet Stuttgart Fakultaet Informatik Postfach 10 60 37 D-7000 Stuttgart 10 Germany e-mail: braunl@informatik.uni-stuttgart.de Name: (first, last) .................................................. Company: (if any) .................................................. Address: (street) .................................................. (city, ZIP) .................................................. (country) .................................................. E-mail: .................................................. Intended Use of Parallaxis: .................................................. .................................................. .................................................. .................................................. Application Areas: .................................................. .................................................. .................................................. .................................................. -------------------------------------------- | This is a [REGISTRATION] / an [ORDER] . | (please mark) -------------------------------------------- (please make sure to accompany order with payment!) [ ] Parallaxis User Manual (order) Computer systems used: .................................................. (floppies ordered, resp.) .................................................. .................................................. .................................................. Thank you for your cooperation! --------------------------------------------------------------- ________________________________________________________________________________ Blitzen Simulator ________________________________________________________________________________ Hello, Last week a notice about the Blitzen Simulator and Tutorial Package was posted. [Blitzen is a massively parallel SIMD machine.] An additional technical report useful to those doing serious programming on the simulator is now available, and an ftp site has been established. Over 120 people have requested the Blitzen package so far (if you did you should have received it by now). Because of the large demand, an anonymous ftp directory has been established on the machine "mcnc.mcnc.org". Use ftp with a user name of "anonymous" and a password of "guest", cd into the directory named "pub", and cd into the directory named "blitzen" to get to it. Currently you will find three files in this directory: 1) an "Index" file that describes the contents of the directory, 2) a file named "blitz.pkg" containing the Blitzen Simulator and Tutorial Package, and 3) A file named "blitz_tr" containing the MCNC technical report entitled "Processing Element and Custom Chip Architecture for the Blitzen Massively Parallel Processor". This report provides an in-depth look at the architectural features of Blitzen, and can probably be considered "essential" if you are planning to do serious Blitzen programming. If you have questions, or if you are unable to use ftp and would like a copy of the simulator package or the technical report, please send email to "brain@adm.csc.ncsu.edu". Thank You, Marshall Brain. ------------- Below is a copy of the original package announcement: Hello, There is now available a free package containing a simulator, tutorials and example code for a massively parallel SIMD machine named "Blitzen". Blitzen was developed for NASA as a follow-on to the MPP by a group of folks from NCSU, UNC, Duke and MCNC. The package is intended to allow students and other people interested in learning about massively parallel architectures to get hands-on experience with a SIMD machine. The simulator will compile and run on just about any Unix system. The tutorials introduce you to the Blitzen architecture (which is very similar to the MPP architecture), the SIMD mindset, and a fairly large amount of example code that exercises different features of the architecture. There is also some image processing code included in the package. The package would make a nice core for a class on massively parallel machines. This package was created to consolidate the simulator and some tutorial information for students learning about Blitzen here at NCSU. It is being made publicly available in the hope that other unversities and companies can use it to give students exposure to massively parallel SIMD architectures. These architectures are becoming more popular, but the scarcity of Connection Machines and MPPs tends to limit student access to these systems. The availability of a free, portable and easy-to-install simulator might help to remedy the situation. If you are interested in receiving the package, you can send email to: brain@adm.csc.ncsu.edu I will ship you the package by return email. Thanks, Marshall Brain. ________________________________________________________________________________ mpsim portable hypercube simulator Dunigan ORNL dunigan@msr.epm.ornl.gov ________________________________________________________________________________ MPSIM Portable (to most UNIX systems) message-passing simulator that supports both C and FORTRAN. Uses forks and pipes to support up to 8 to 16 processes on UNIX BSD 4.x, SYS V 3.x, DYNIX, Encore, Ultrix, Sun, XENIX, Tek UNIX, 3B2s. Simulates Intel iPSC/1 and iPSC/2 hypercubes and produces trace file of message events. Trace-file analyzers produces tabular or graphical summaries. (Encore and Sequent versions will utilize multiple processors.) top directory contains sample programs and trace file postprocessors (nstats.c, ccplot.c, trace1.c) src/ the beef, do a make here to create mpsim and simlib.a mpsim.man and makefiles; also sample build scripts (sbld, sfbld) --------------------------------------------------------- Information on other ORNL parallel processor simulators ORNL parallel processor simulators dunigan last change: 8/3/88 directories: (source distribution size) mpsim/ portable simulator, sample programs (122KB) src/ mpsim source smpsim/ sequent version (NS32x32) of mpsim using shared memory (147KB) sysVsmpsim/ beta version of mpsim using System V shared memory (62KB) ppsim/ interpretive simulator (2.8MB) doc/ man entries and such postp/ postprocessor of trace files samples/ sample codes lll/ original LLNL distribution seqdn/ version of simulators for Sequent (32032 CPUs only) kernel/ library source, aspp source local/ sample bld and makefile for applications sundn/ version of simulators for Sun workstations (Sun 3/68881 only) kernel/ library source, aspp source local/ sample bld and makefile for applications vaxdn/ version of simulators for VAX UNIX 4.x/Ultrix kernel/ library source, aspp source local/ sample bld and makefile for applications Simulator summary: We have several hypercube simulators and a simulator for shared-memory parallel processors; all support C and Fortran. A brief summary: Name Runs on Granularity Performance Debugging Info Help ppsim Vax, Sequent, Sun fine yes yes mpsim Any Unix with pipes coarse no yes smpsim Sequent coarse no yes PPSIM Interpretive parallel processor simulator, based on "Multitasker" by Eugene Brooks, modified to support message-passing parallel processors. Provides instruction level tracing, program tunable message-passing parameters (startup time, node-to-node rates, host-to-node rates, packet size). Trace file post-processing programs provide concurrency plots and tabular summary of message passing behavior. Supports C and f77 on UNIX 4.x on VAX, Sun 3 (68020/68881), or Sequent (32032) processors. Message-passing software emulates Intel iPSC/1 hypercube subroutines. Shared-memory simulation supports, locks, events, barriers, semaphores, enqueue, and task creation. We have used this package in teaching graduate course in parallel programming. SMPSIM MPSIM converted to use shared-memory of Sequent for message passing. The above table is a bit of an over simplification, of course. ppsim gives an interpretive simulation at the level of individual instructions and has tunable performance parameters. It runs as a single process under Unix and gives meaningful, graphical performance output and is also useful for debugging. mpsim uses multiple Unix processes communicating via pipes. It is helpful for debugging but doesn't give very meaningful performance info. Its advantage over ppsim is faster execution (in terms of wall clock time). smpsim is a specialization of mpsim to the Sequent in which communication by pipes is replaced by communication via shared memory, which is much faster still. In fact smpsim simulates an iPSC in faster than real time for the same number of (real) processors. Documentation: man entries are included in the various distribution directories. Additional technical reports: "A message-passing multiprocessor simulator",Dunigan, ORNL/TM-9966 "A portable hypercube simulator", Dunigan, ORNL/TM-10410 "Denelcor HEP multiprocessor simulator, Dunigan, ORNL/TM-9971 "A multitasking kernel for the C and Fortran programming languages", Brooks, LLNL UCID-20167 Work-in-progress: dcube-- hypercube simulator using TCP/IP-connected workstations as the nodes "Hypercube Simulation on a Local Area Network", Dunigan, ORNL/TM-10685 dunigan@msr.epm.ornl.gov ________________________________________________________________________________ Reconfigurable Architecture Workbench Walt Ligon ________________________________________________________________________________ I have been working on a parallel architecture simulator, the Reconfigurable Architecture Workbench (RAW) that might be of interest to you. RAW allows you to write programs using C and execute them as if on a wide variety of different parallel architectures. The programs are compiled to an architecture independent code (AIC) and then compared to an architecture description code (ADC) at execution time in order to determin the performance of the program. RAW will simulate the following types of architectures: SIMD machines, MIMD machines, as many or as few processors as you have memory to simulate (I have simulated 8192 SIMD processing elements requiring about 25M of main storage, MIMD processing elements require a bit more storage), shared memory or message passing, and just about any kind of network you can imagine. currently I don't have a cache simulator installed, but there are folks working on that. RAW has been used by a number of students to develop parallel programs in both SIMD and MIMD modes using a wide variety of the features mentioned. The biggest problem with you using RAW is that RAW is not a production piece of software, only a small part of the C library is implemented, documentation is minimal, and debugging facilities are almost non-existant. There is also no guarantee that a student won't encounter a bug that is not his fault at all and there is no support whatsoever for RAW (other than sending me mail and asking if I have time to look at the problem). Not to be too pessemistic. Like I said, a number of students have successfully implemented programs with little or no problems at all. I'm not sure I'd throw 100 green-horns at it, but it might make an interesting tool to take out for a test drive for a group of motivated students (IOW I wouldn't stake the entire course on it just yet). Actually, I am very interested in getting the rough edges smoothed off and having the system exercised more fully. If you were to get excited about it, we could discuss getting some of the remaining parts finished off by myself, some of the students here, and maybe some of your graduate students who are into system software stuff. Really, most of what is needed is pretty simple but time consuming stuff that I haven't really needed, so I haven't taken the time to get it all squared away. Anyway, if you want to know more, drop me a line, I can send you a paper about it or even arrange for you to get the code. Let me know. Walt Ligon walt@cc.gatech.edu ________________________________________________________________________________ Image Understanding Architecture Simulator Jim Burrill ________________________________________________________________________________ We can make available to you a simulator for the first generation of the Image Understanding Architecture that runs under SunOs 4.1 on a Sparcstation or Sun4. The Image Understanding Architecture is a massively parallel computer utilizing a SIMD grid of bit serial processors at the bottom level and a MIMD grid of TI TMS320C25 DSP processors at the intermediate level. Programs to be run on the simulator may be written in Forth & C for the SIMD level and Assembler or C for the intermediate level (you must obtain the C25 C compiler from TI). You can read about this system in "Parallel Architectures and Algorithms for Image Understanding" ed by V.K. Prasanna Kumar, Academic Press, 1991. Jim Burrill burrill@aai.com ________________________________________________________________________________ Tango System Stephen Goldschmidt ________________________________________________________________________________ There are two published tecnical reports on Tango: CSL-TR-90-410 Tango Introduction and Tutorial CSL-TR-90-439 Tango: A Multiprocessor Simulation and Tracing System You may obtain an unofficial PostScript copy of these reports via anonymous FTP from meadow.Stanford.EDU (36.64.0.20). The files are in the /tango directory (tutorial.ps and methodology.ps). Also, there is a paper on Tango in the Proc. ICPP of 1991: Multiprocessor Simulation and Tracing Using Tango If you have specific questions, send them to me at: comments@meadow.Stanford.EDU The Tango code is property of Stanford University. To obtain the source code, you must also obtain a Stanford Academic License Agreement from: Stanford University / Office of Technology Licensing 857 Serra Street, Second Floor Stanford, CA 94305-6225 tel: (415) 723-0651 fax: (415) 725-7295 email: otl@popserver.Stanford.EDU I cannot send Tango source to you until you have returned a signed copy of this Agreement. (Note that we currently do not distribute Tango outside the United States.) Media available are: reel-to-reel tape (1600 bpi), cartridge tape (60 Mb), and uuencoded electronic mail. Please be aware that Tango only runs on machines that use Mips processors. Versions are available for Ultrix (DecStations), Irix (SGI machines), and UMips (Mips M/120). Porting Tango to a Sun or Vax architecture would be a major undertaking. Stanford does not provide any support for Tango. This is prototype code and is not an efficient implementation. A more efficient replacement for Tango, using lightweight threads and running as much as 50x faster, has been developed at Stanford, but is not being distributed. Stephen Goldschmidt, Tango Guru, comments@meadow.Stanford.EDU ________________________________________________________________________________ > From: gwilson@umiacs.UMD.EDU (George Wilson) 1. There is a StarLisp simulator for the Connection Machine that I believe is in the public domain. I believe it can be had by anonymous ftp from think.com. ________________________________________________________________________________ > From: hlv@think.com (Harry Voorhees) Thinking Machines is pleased to announce that the latest *Lisp Simulator is freely available. The *Lisp Simulator is a simulator for *Lisp, one of the programming languages used to program the Connection Machine. Thinking Machines provides free, with the *Lisp Simulator, an on-line 'Getting Started in *Lisp' manual. This manual is also available in hardcopy without charge from Thinking Machines (see ordering *Lisp documentation below) The *Lisp Simulator is available via anonymous ftp in the /public directory of think.com in the subdirectory /cm/starlisp. The file that can be ftp'ed is a Unix 'shar' file called starsim-f19-sharfile or starsim-f19-sharfile.Z (where f19 may be replaced in the future by a higher release number) The F19 version of the *Lisp Simulator is compatible with the latest *Lisp software (version 6.1) for the Connection Machine hardware. It is written in portable CLtL I. This sharfile provides the necessary sources and systems for the *Lisp Simulator to run under Symbolics, Lucid, Allegro and Franz Common Lisps. Porting the *Lisp Simulator to other Common Lisp's is generally a simple matter. The 'Getting Started in *Lisp' manual is available free of charge. Other documentation for the *Lisp language is available at cost from Thinking Machines Corporation. The *Lisp Reference Manual and the Dictionary together are $100. Send a request and/or a check or a purchase order to: Thinking Machines Corporation 245 First Street Cambridge, MA 02142-1264 Attn: Katy Smith Or by sending e-mail to: Internet: documentation-order@think.com uucp: harvard!think!documentation-order Note: People wishing to distribute the *Lisp Simulator should distribute it using the sharfile in /public and not from the sources provided on-site at Connection Machine customer installations, since these sources do not provide all the documentation, instructions and auxiliary files useful in installing the *Lisp Simulator at a non Connection Machine site. Caveat: Thinking Machines will continue to provide support for the *Lisp Simulator for Thinking Machine's Connection Machine customers. Thinking Machines is under no obligation to provide support for other users of the *Lisp Simulator, either in porting or using it. Return-Path: pgraham@silver.cs.UManitoba.CA Received: from bank.ecn.purdue.edu by en.ecn.purdue.edu (5.65/1.32jrs) id AA05912; Wed, 9 Sep 92 10:35:04 -0500 Received: from ccu.umanitoba.ca by bank.ecn.purdue.edu (5.65/1.32jrs) id AA27588; Wed, 9 Sep 92 10:34:59 -0500 Received: from silver.cs.UManitoba.CA by ccu.UManitoba.CA (4.1/25-eef) id AA23605; Wed, 9 Sep 92 10:34:53 CDT Received: by silver.cs.UManitoba.CA (4.1/25-eef) id AA09051; Wed, 9 Sep 92 10:34:59 CDT From: Peter Graham Message-Id: <9209091534.AA09051@silver.cs.UManitoba.CA> Subject: Re: Wanted: Public Domain parallel machine simulators To: picano@ecn.purdue.edu (Silvio Picano) Date: Wed, 9 Sep 92 10:34:59 CDT In-Reply-To: <9208172128.AA00810@en.ecn.purdue.edu>; from "Silvio Picano" at Aug 17, 92 4:28 pm X-Mailer: ELM [version 2.3 PL11] Status: O Hi, I had two replies to my recent query about parallel simulators which might be of interest to you. Here they are: ================================================================================ Message 32/138 From Norm Matloff Aug 20 '92 at 5:39 pm -420 Return-Path: Date: Thu, 20 Aug 92 17:39:12 -0700 To: pgraham@cs.umanitoba.ca Subject: parallel machine simulators Cc: matloff@cs.ucdavis.edu I've been working on a simulator for shared-memory multiprocessors. The basic instruction set is similar to (but not the same as) that of the SPARC architecture. The program is modular, so that any type of processor-memory interconnect (bus, omega-net, etc.) can be simulated, by changing just one module. Programming in the simulated system must be done in the assembly language of the simulated processor (no compiler yet). For teaching purposes, this is probably best anyway, so the students can see how the machine resources are being used, where contention occurs, etc. I have a prototype version working now. If you are interested, I could send it to you (please state what machine you wish to run it on). Norm Matloff matloff@cs.ucdavis.edu ================================================================================ Message 47/138 From W. Bernard Lee Aug 17 '92 at 11:18 pm pdt Return-Path: Subject: parallel machine simulators To: pgraham@cs.umanitoba.ca Date: Mon, 17 Aug 92 23:18:08 PDT Re your posting to comp.parallel, we have perhaps one of the best simulators at Stanford that run iPSC/860 code on SGIs with BETTER speed-ups than the real Intel. The simulator is developed by the Stanford DASH project with help from the NASA Ames Research Center. It will be upgraded soon to run on a network of workstations and there are also parallel efforts at major European centers to integrate our library to other major parallel computation protocols in Europe. The library is available via anonymous FTP from: mojave.stanford.edu: /pub/dash-msg-library Please read the legal notice prior to downloading. Regards, Bernard Lee Stanford CS Dept ============================ Message 41/138 From bernardl@vnet.ibm.com Aug 18 '92 at 1:00 pm pdt Return-Path: Date: Tue, 18 Aug 92 13:00:24 PDT To: pgraham@cs.umanitoba.ca When we have the socket-based i/o running I don't think much of the library will be SGI-dependent. i.e. -- you can just run it off a network of workstation. It is likely that we will have that available by the end of the summer, although we may not have the manpower to do the final integration on non-SGI workstations for you. -- BERNARD ================================================================================ Many thanks to you for your contribution as well. Cheers, Peter. -- Peter C.J. Graham Computer Science (204) 474-8313 University of Manitoba, Winnipeg MB Canada R3T 2N2 >From en.ecn.purdue.edu!noose.ecn.purdue.edu!mentor.cc.purdue.edu!purdue!ames!haven.umd.edu!uunet!gatech!hubcap!fpst Wed Sep 16 15:44:24 EST 1992 Article: 3840 of comp.parallel Xref: en.ecn.purdue.edu comp.parallel:3840 comp.edu:3165 Path: en.ecn.purdue.edu!noose.ecn.purdue.edu!mentor.cc.purdue.edu!purdue!ames!haven.umd.edu!uunet!gatech!hubcap!fpst From: matloff%mole.Berkeley.EDU@ucbvax.Berkeley.EDU (Norman Matloff) Newsgroups: comp.parallel,comp.edu Subject: ANNOUNCEMENT: Multiprocessor Simulator Message-ID: <1992Sep16.122505.24743@hubcap.clemson.edu> Date: 15 Sep 92 18:14:25 GMT Sender: nobody@ucbvax.Berkeley.EDU Organization: UC Davis Division of Computer Science Lines: 41 Approved: parallel@hubcap.clemson.edu MulSim Multiprocessor Simulator Norman S. Matloff University of California at Davis Division of Computer Science matloff@heather.cs.ucdavis.edu (916) 752-1953 MulSim simulates the operation of a shared-memory multiprocessor system. Its processor type is of a RISC design largely similar to the SPARC architecture -- i.e. instructions execute in a single cycle, and it is a load/store machine, with all arithmetic operations being done in register-to-register mode only -- with a system of register windows being used to store the runtime stack. User programs are written in the assembly language for this architecture. The user may choose from several types of processor/memory interconnects, or may develop his/her own type of interconnect; MulSim has been designed in a modular fashion which facilitates the user taking the latter approach. There are also optional features which allow the user to do statistics-gathering, etc. The system includes a fairly extensive debugging facility, which can be used not only for debugging but also for close examination of program behavior, e.g. to help identify how memory contention problems arise. ******************************************** The MulSim system is available free of charge for noncommercial use, e.g. in universities. To obtain a copy, please send e-mail to matloff@heather.cs.ucdavis.edu Be sure to specify the type(s) of host machine you wish to run MulSim on (presently it is available for SPARCstation, DECstation and DOS systems). Subject: New Release of SPIM (v 5.0) Reply-To: larus@cs.wisc.edu Date: Wed, 23 Sep 92 09:33:22 CDT From: James Larus Status: O I have just released a new version (version 5.0) of SPIM/XSPIM, which is a detailed simulator of the MIPS R2000/R3000 processors (see detailed description below). This is a major release. Everyone using SPIM should use this version as soon as possible. Along with the usual assortment of bug fixes and improvements, this release includes the following significant changes: 1. SPIM/XSPIM is no longer covered by the GNU copyleft. It is now distributed under narrower terms that only prevent you from selling or distributing SPIM/XSPIM with a product. 2. The binary mode SPIM/XSPIM (which runs MIPS executables) is greatly improved thanks to Emin Gun Sirer, Andrew Appel, Scott Rosenberg, and Anne Rogers of Princeton and will now run many or most MIPS binaries. 3. SPIM/XSPIM now includes an optional cycle-level simulator that does a detailed, cycle-by-cycle simulation of the MIPS pipeline. Thanks to Scott Rosenberg and Anne Rogers for this code. 4. A number of significant bugs that affect the correctness of the simulation have been fixed. These alone are a good argument to move to the new version. 5. SPIM/XSPIM now has a simple memory mapped I/O facility inspired by John Ousterhout's MIPSIM. 6. The source for SPIM/XSPIM now has a new home. You can ftp SPIM/XSPIM from ftp.cs.wisc.edu in the file pub/spim/spim.tar.Z SPIM/XSPIM is no longer kept on my home machine. /Jim Computer Sciences Department 1210 West Dayton Street University of Wisconsin Madison, WI 53706 larus@cs.wisc.edu 608-262-9519 The SPIM S20 is a software simulator that runs assembly language programs for the MIPS R2000/R3000 RISC computers. SPIM can read and immediately run files containing assembly language statements. It can also read and run MIPS a.out files (when compiled on a MIPS system). SPIM is a self-contained system for running these programs and contains a debugger and interface to the operating system. I wrote SPIM as the target machine for an undergraduate compiler course. SPIM is very portable (I have run it on a DECStation 3100/5100, Sun 3, Sun 4, PC/RT, HP Bobcat, and Sequent***), so the students could generate code for a simple, clean, orthogonal computer; no matter which god-awful machine they used. It was a very successful in this role. SPIM is fairly slow. It runs about 1000 dhrystones/second, which is roughly 1/25th the speed of a DECStation 3100, or about the speed of a 68010-based system. SPIM implements almost the entire MIPS assembler-extended instruction set (I've omitted some the complex floating point comparisons and details of the memory system page tables). SPIM comes with complete source code and documentation of all instructions (including several that aren't in Kane's book, but are produced by MIPS compilers). It also include a large torture test to verify a port to a new machine. SPIM has a simple, terminal-style and a flashy, X-windows interface. SPIM also includes an optional extension by Anne Rogers and Scott Rosenberg of Princeton that performs a cycle-by-cycle MIPS simulation that exposes the hardware pipeline. SPIM is copyrighted by me and can be freely used for non-commericial purposes. You can copy a compressed tar file from ftp.cs.wisc.edu in the file: ~ftp/pub/spim/spim.tar.Z. If you want to be informed of future updates, send me your electronic address. /Jim James Larus Computer Sciences Department 1210 West Dayton Street University of Wisconsin Madison, WI 53706 larus@cs.wisc.edu (608) 262-9519 *** SPIM also runs on a VAX, however it does not handle floating point properly because compilers for the VAX do not treat single floats properly. $Header: /home/primost/larus/RCS/BLURB,v 1.2 1992/09/18 02:26:24 larus Exp larus $ FROM: D.J. Jackson The following information consists of all the responses I got from my request for simulator information. I'm sorry that I have not had time to format these responses properly but school has started here and all of my free time has vanished. I have even left in the me-too responses so everyone would have some idea of others that are interested in the status of simulators. Everything that follows is the verbatum responses I received. If I can be of further assistance, please let me know at jjackson@tiger.carl.ua.edu or (205) 348-2919. David Jeff Jackson **BEGIN*RESPONSE*LIST************************************************************* >From picano@tazdevil.llnl.gov Thu Jul 30 21:31:13 1992 Return-Path: Received: from carlrs6000.carl.ua.edu by tiger.carl.ua.edu (4.1/SMI-4.1) id AA01944; Thu, 30 Jul 92 21:31:12 CDT Received: from tazdevil.llnl.gov by carlrs6000.carl.ua.edu (AIX 3.2/UCB 5.64/4.03) id AA13427; Thu, 30 Jul 1992 20:59:21 -0500 Received: by tazdevil.llnl.gov (4.1/1.15) id AA03181; Thu, 30 Jul 92 19:30:32 PDT Date: Thu, 30 Jul 92 19:30:32 PDT From: picano@tazdevil.llnl.gov (Silvio Picano) Message-Id: <9207310230.AA03181@tazdevil.llnl.gov> To: jjackson@carlrs6000.carl.ua.edu Subject: Re: Availability of RISC simulators? Newsgroups: comp.arch In-Reply-To: <1992Jul30.175743.113288@ua1ix.ua.edu> Status: RO In article <1992Jul30.175743.113288@ua1ix.ua.edu> you write: > >I am interested in compiling a list of all RISC simulators which run under some >form of UNIX O.S. (preferably BSDish) and are available at no cost (or minimal Here are some additions (88110, AMD, and SPARC simulators with some comments I plucked from the UseNet). When you get a full list, please pass it on to me. Thanks. Silvio =========================== =========================== >From noose.ecn.purdue.edu!samsung!cs.utexas.edu!oakhill!phillip Tue Nov 12 10:28:46 EST 1991 Article: 11074 of comp.arch Xref: en.ecn.purdue.edu comp.arch:11074 comp.sys.m88k:723 Path: en.ecn.purdue.edu!noose.ecn.purdue.edu!samsung!cs.utexas.edu!oakhill!phillip From: phillip@oakhill.sps.mot.com (Mike Phillip) Newsgroups: comp.arch,comp.sys.m88k Subject: Re: 88110 presentation at Microprocessor Forum Message-ID: <1991Nov11.161245.9832@oakhill.sps.mot.com> Date: 11 Nov 91 16:12:45 GMT References: <11518@spim.mips.COM> <4xdH5b8q3@cs.psu.edu> Reply-To: oakhill!phillip@cs.utexas.edu (Mike Phillip) Followup-To: comp.arch Organization: Motorola Inc., Austin, Texas Lines: 134 In article <4xdH5b8q3@cs.psu.edu> melling@cs.psu.edu (Michael D Mellinger) writes: > >What are the SPECmarks for the 88110, and at what clock speed was the >chip running? > [Warning... long explanation ahead to help avoid excessive flaming for presenting simulated performance figures.] The SPEC data that Keith presented at Microprocessor Forum was based on simulations of the 88110 at a clock speed of 50 MHz. The simulator (XSim) is an extremely accurate instruction-level model of the chip that presents timing information on a clock-by-clock basis. It models virtually every microarchitectural feature of the chip, including on-chip instruction and data caches and PATC (TLB) timing effects. External memory is modeled using user-definable parameters that specify two "delay" factors (in clocks) corresponding to the critical word off-chip memory access and subsequent "burst" accesses for the remainder of the cache line fill. The simulator has been available as a Motorola product (under non-disclosure agreement) to interested parties for well over a year now, and can execute either SVR3 (COFF) or SVR4 (ELF) binary formats. Since the simulator was developed in parallel with the chip itself, a great deal of effort was made to verify the accuracy of the simulator by comparing timing sequences with the actual chip design models. Of course, external memory and system effects are difficult/impossible to verify on chip models, which is why the external memory modeling in the simulator was designed to be fairly flexible. For the data reported below, the 88110 SPEC code was compiled using an Alpha release of the Motorola 88110 C and Fortran compilers. No "hand-tuning" or modification of assembly code took place when compiling SPEC, so the performance is truly a function of the chip/compiler/system combination, not a speadsheet. I won't go into a lot of justification/explanation of the value of simulated performance, as I think this ground was thoroughly covered a few weeks ago for the R4000. The bottom line is that we believe that we have the capability to accurately model the 88110 in software, and we have been able to make extensive use of the simulator to tune performance of the compilers. It should go without saying (but I'll say it anyway) that these numbers should not be taken as being absolutely representative of any particular implementation of an 88110 system. The limitations/features of the simulation environment should be taken into account, and ultimately, the "official" figures will be based on actual hardware. Draw your own conclusions... That being said, here are the numbers presented at Microprocessor Forum and a detailed summary of the environment used for the simulations: ------------------------------------------------------------------ Simulated 88110 SPEC Performance (SPEC Release 1.2) ------------------------------------------------------------------ (Single chip implementation @ 50 MHz; no secondary cache) gcc 46.5 espresso 48.1 spice 34.7 doduc 41.4 nasa7 67.9 xlisp 57.0 eqntott 52.9 matrix300 357.8 fpppp 64.4 tomcatv 72.2 Geometric Mean (Integer) 51.0 Geometric Mean (Flt. Pt.) 73.9 Overall simulated SPECmark: 63.7 ------------------------------------------------------------------ Notes: - All simulations based on XSim (RISCit Version 1.1) - An 88110 clock speed of 50 MHz was assumed. - On-chip caches were fully modeled in "copyback" mode. (8 Kb data, 8 Kb instruction; two-way set associativity) - No secondary cache was used. (We can approximately model an "infinite" secondary cache as 3/1 memory, but felt that the resulting performance figures would be skewed too much to be taken seriously... future releases of the simulator will include secondary cache modeling capabilities. Generally speaking, we've been seeing 20-25% improvement when a reasonably large secondary cache is used) - "Infinite" external DRAM memory was assumed. (not too bad an assumption for SPEC 1.2 on next-generation systems...) - External DRAM memory was configured as 9/1 (180 ns off-chip delay to access critical word, 20 ns for each subsequent burst access in the line fill - i.e. 9 clocks/1 clock == 9/1) - PATC (Page Address Translation Cache) misses were modeled by adding 29 clocks (= 580 ns) to the subsequent critical word memory access. This approximately simulates a "tablewalk" effect... - All benchmarks were simulated in their entirety; functional results were verified to be correct. For the xlisp and spice benchmarks, the "short" versions of the SPEC benchmarks were simulated and resultant "long" execution times were extrapolated using the ratio of long/short times on a 25 MHz DG 88100 Aviion server. (The "long" versions were simply too large to simulate in a reasonable amount of time on XSim) - All code was compiled using Motorola 88110 compilers (Alpha release 1.3) except xlisp, which was compiled using the Diab 88110 C compiler (2.37) (Strictly a performance issue...) - A prototype of the Kuck and Associates preprocessor was used in conjunction with the Motorola compilers for the matrix300 and nasa7 benchmarks. - Reported performance figures do not account for system time. (Again, we believe this to be a minor factor for the very CPU-intensive SPEC 1.2 benchmarks. Other system factors may also have a slight negative impact on actual performance). In a nutshell, we believe, from a technical point-of-view, that these numbers portray an accurate "snapshot" of where we are at in terms of 88110 compiler/chip performance. System effects that degrade performance as currently reported will likely be offset by ongoing compiler improvements. The memory system parameters were chosen to be typical of 88110 systems that are under development. Finally, in anticipation of the inevitable "that's nice, but when can we buy one?" questions, don't ask - I can't answer the question, and I doubt anyone else will, either. Flame if you want, but the choices are (a) a technical discussion of the Microprocessor Forum presentation or (b) nothing at all. I've heard valid arguments for both, so spare me, please... :^) -------------------------------------------------------------------------- Mike Phillip E-mail: phillip@oakhill.sps.mot.com RISC Compiler Development or oakhill!phillip@cs.utexas.edu Motorola, Inc. Austin, TX Phone: (512) 891-3656 -------------------------------------------------------------------------- >From article <92-02-066@comp.compilers>, by dornic@ensmp.fr (Vincent DORNIC): > Does someone knows if there exists a complete chain for the AMD 29000 > processor? It must consist in a C compiler, a linker, an emulator and a Metaware has a compiler package (C and C++). AMD offers this package along with a simulator and symbolic debugger. You should probably talk to AMD representative directly. He/She should be able to give you the necessary ordering information. Gene Yurek att!hrmsc!ejy ---------------------------------------------------------------------- Yes, AMD offers a package, but EPI's is more complete and more customizable. I am a customer of EPI, and just purchased their system. They are in Sunnyvale or Santa Clara California. I think their number is (408) AM29000 -- mac@kpc.com ---------------------------------------------------------------------- ---------------------------------------------------------------------- I am currently using Robert Bedichek's 88100 simulator, g88. It is actually an emulator of the MVME188 Hypermodule, a 4-CPU 8-CMMU 88k system. It emulates many of the system devices and interrupt structure. So any program I write for the real hardware will run unchanged on the simulator The front end it uses is gdb3.1. Running anything under the 88k simulator is just like running anything else in gdb. Other features it includes is cross-debugging support to the real MVME188 hardware. g88 is available via public ftp from cs.washington.edu I think. You can contact Robert at robertb@cs.washington.edu -- I'm sure he'd like to hear from anyone interested in his simulator. Interested by Rob's work on g88, Peter Magnusson (psm@sics.se) has developed new designs for CPU simulators. I believe he is implementing his ideas in a new version of the 88k simulator. He has submitted a paper to MASCOTS '93 -- looks like some good stuff. I am developing an SMP micro-kernel for the MVME188. This kernel will be used as run-time support for high-speed networking projects and object oriented parallel language research. g88 allows me to debug the kernel either on the simulator or on the real hardware, using the standard gdb interface (I haven't bothered with an X interface). Cheers, Stuart ---------------------------------------------------------------------- If you haven't already heard from robertb@cs.washington.edu (Robert Bedichek), drop him a line. He's done extensive work with simulators that is surely free to .edu types. jas ---------------------------------------------------------------------- You are welcome to my 88k simulator, in g88.tar.Z along with tools88.tar.Z on cs.washington.edu. There is the postscript for a paper on the simulator in g88.usenix.ps.Z from the 1990 Winter USENIX. There are more papers by psm@sics.se that extend my stuff for parallel machines. g88 is in daily use by several groups, so it is pretty robust. It has run System V.3.2 and currently runs Mach 2.5 and 3.0 + OSF/1. There may be some initial pain with the tools. Let me know if I can help. "I have a R2000 simulator and I have SPARC and RS/6K hardware, so my "pressing need is for the M88K, AMD and Intel processors. There is definitely an i960 simulator, you might try Konrad Lai at Intel in Hillsboro, or the people at Intel who provide i960 GNU tools. But it isn't fast and its front end is not a symbolic debugger. "I am using these in a graduate RISC class so I hope that .com people, "or others, would agree the the "free" requirement. "Can you help with any list/suggestions/contacts? Let me know how it goes. Rob