Introduction to SPARC Assembly Language
Mark Smotherman
Clemson University




Program translation

  symbolic (i.e., human readable) languages

    high-level language (HLL)

    assembly language - one-to-one (approx.) correspondence with machine
                        instructions which are represented inside the
                        computer in bit (0/1) patterns


  translators from one language level to a lower level

    compiler  - HLL to assembly

    assembler - assembly to object file

    linker    - bind multiple object files into one executable file

  each moves closer to the bit representation needed by hardware for execution


Assembly

  a statement in assembly language is called an instruction

  an instruction is composed of

     - operation code (opcode)

     - operands       (names of registers and/or
                      information needed to generate a memory address)


  example: SPARC assembler

    SPARC symbolic code       ------->  address  machine code (in hexadecimal)
    -------------------                 -------  ------------
    main:
	save %sp,-104,%sp		0x10a50  0x9de3bf98
	mov 9,%l0			0x10a54  0xa0102009
	add %l0,-1,%l1			0x10a58  0xa2043fff
	add %l0,-7,%o1			0x10a5c  0x92043ff9
	mov %l1,%o0			0x10a60  0x90100011
	call .umul,0			0x10a64  0x400042fd
	nop				0x10a68  0x01000000
	add %l0,-11,%o1			0x10a6c  0x92043ff5
	call .div,0			0x10a70  0x400042fd
	nop				0x10a74  0x01000000
	mov %o0,%l1			0x10a78  0xa2100008
	ret				0x10a7c  0x81c7e008
	restore				0x10a80  0x81e80000


  labels (like "main" above) represent symbolic addresses of data and jump
     targets in the program

  each label must be unique (i.e., it must be defined only once)


Assemblers have a two-pass structure

  instructions can have forward or backward references to labels

  note that a forward reference requires a two-pass assembly structure since
     you encounter a "use" before its "definition" and thus cannot immediately
     translate the label into its memory address

  thus:

    pass 1 - increment a location counter as you read each assembly language
                statement and collect any label definitions into a symbol table
                with the corresponding location counter values

    pass 2 - translate the assembly language statements using the symbol table


  alternatively, if you keep all the translated code in memory, you can
    translate in one pass over the input -- but you must keep a record of
    all unresolved uses of a label (e.g., the symbol table entry for an
    as-yet-undefined label points to a linked list of all forward references)
    and then you backtrack and fixup those uses whenever the definition is
    encountered


SPARC - Scalable Processor ARChitecture

  load/store architecture - only load/store instructions can access memory

  69 basic instructions (all fixed length -- one word each = 32 bits)

  derived from RISC work of David Patterson at Univ. of California at Berkeley

  designed for efficient pipelined implementation (e.g., delayed branch)

  32 registers (plus register windows)
	8 global -- %r0 == %g0 always returns zero
	8 out    \
	8 local   > register windows allow previous outs to overlap current ins
	8 in     /


Comparison and contrast of SPARC and Intel x86 (used in original IBM PC)

  similarities:

		8-bit bytes (allows representation of ASCII-encoded character)
		byte-addressable memory (address down to individual character)
		two's complement for signed integers
		floating point follows IEEE standard
		arithmetic, logical, and shift operations
		branching and calling instructions
		condition codes used for branch decisions
		stack frame support (sp, fp/bp) for procedure calls
		can be pipelined and have superscalar implementations

  differences:

	SPARC					 x86
	(version 7)				(8086)
	-----------				------

  32-bit words				16-bit words

  32 general purpose registers		8 registers, most w/ special purpose
     (more on chip but only 32		   (i.e., have fixed usage in certain
     are visible at any one time)	   operations)

  special register for multiplication   (AX and DX registers fixed usage in
     called Y				   multiplication)

  fixed-length insts. (4 bytes)		variable-length insts. (1-6 bytes)

  load-store architecture		extended accumulator architecture,
     reg-to-reg ops			  reg-to-mem and mem-to-reg ops.

					string insts. with both operands in
					   memory (movs, cmps, ...)

  3-register instruction format:	mainly 2-operand instruction format:
     rA op rB -> rC			   rA <- rA op memory
					   memory <- memory op rA

  floating point uses separate set	floating point uses a separate stack
     of 32 registers

  delayed branches			normal branches

  RISC - reduced instruction set	CISC - complex instruction set computer
     computer => streamlined for	   => complicated operations (some of
     ease of hardware implementation       this is due to legacy, i.e., need
					   for compatibility with previous
					   8080 and 8085 microprocessors)

  big-endian memory addressing		little-endian memory addressing

  requires aligned operands		unaligned operand access in hardware

  linear memory with paging		segmented memory addressing

  two execution modes (OS, user)	no protection

  memory-mapped I/O			I/O instructions (IN, OUT) with port
					   addresses for device registers

				extensions
				----------
  SPARC version 8 - multiply inst.	386 - 32-bit, 4 exec. modes, paging
  SPARC version 9 - 64-bit words	486 - heavily pipelined, on-chip FPU
  HyperSPARC - 2 insts./cycle		Pentium - 2 insts./cycle
  SuperSPARC - 3 insts./cycle		Pentium II and III - 3 insts./cycle
  UltraSPARC - 4 insts./cycle		      out-of-order execution