IBM Advanced Computing Systems -- Draft Design sections

Mark Smotherman
last updated November 21, 2009

under construction
(This reflects my current understanding. I very much appreciate corrections and new material.)


Hardware Design Tools and Design Process

Everything was a daily tradeoff between the capabilities of the compiler (for which Fran Allen and John Cocke are almost solely responsible), the architecture, and the engineering capability. We did it every day ... most individuals were involved in most of the discussions ... it was very fluid ... and the fluidity is why the simulators were so important.

-- Ed Sussenguth, personal correspondence


... to be expanded (e.g., crucial role of simulator in ACS, as in Stretch) ...


Sidebar - chip layout for the Amdahl 470 as compared to ACS

"My plan to use a larger chip size [for the Amdahl 470] for easier interconnection was improved upon by Fred Buelow, who learned there was a discarded, easily routed approach called a gate-array, which wasn't economical enough for chip manufacturers, but we could get a 100 gate chip, Large-Scale-Integration (LSI). This was phenomenal, for the ACS technology only provided about 35 gates, Medium-Scale-Integration (MSI), and took three or four months for a gifted man to route!" [ Gene Amdahl interview, IEEE SSCS E-news, 2007]

"We laid out [the Amdahl 470] chips so they looked just like the same density and the same connectivity requirements as a printed circuit board. We used printed circuit board routing to lay out our chips. This allowed us to get 100 gates on a chip, which was the first time that had been done. In ECL, the largest number anyone had ever done before was something like 35 gates, and that took normally about six or seven months to lay out. If there was a mistake, it would take another three or four months to fix it. But we laid these out in a matter of days using high-performance IBM 1130s for routing chips." [Gene Amdahl interview, IEEE Design and Test of Computers, 1997]


Hardware Design Schedule as of mid-1967

design timeline

Acknowledgements: Thanks to Bill Mooney for providing the design schedule, to Jim Frego for information about the wiring and testing of modules, and to Jack Powers for the information about CUDC.


Navigation within IBM ACS pages:

Back to first ACS page

Next sections: Compiler / Performance