Clemson University -- CSPC 231 -- Fall 2010 -- Study Guide for Exam 1 First exam covers chapter 1. 1. Be able to define the terms in the glossary on pages 45-46. ALU (arithmetic/logic unit) registers memory CPU (central processing unit) machine language assembly language PC (program counter) von Neumann cycle (fetch/execute cycle) macro processor eval define stack machine JVM (Java virtual machine) accumulator machine load/store machine assembler label symbol table location counter Also be able to define these additional terms: address MAR (memory address register) MDR (memory data register) IR (instruction register) opcode mnemonics object code instruction load store branch pseudo-op (K) kilo- (m) milli- (M) mega- (greek mu) micro- (G) giga- (n) nano- (T) tera- (p) pico- (P) peta- direct addressing immediate indirect addressing indexed addressing 2. Be able to work exercises like 1-1, 1-2, and 1-3 on pages 46-47. 3. Be able to draw a diagram of a simple computer system and label these parts: CPU, cache, bus, memory, I/O controller, I/O device. 4. Be able to explain why forward references require a two-pass structure for a translator. 5. Be able to explain and/or demonstrate what each pass does for a two-pass assembler. 6. Be able to explain and/or demonstrate how we got the m4 file "assembler.m" to act as a two-pass assembler. 7. Be able to explain m4 built-in functions eval() and ifelse(). 8. Given a math expression or HLL code segment, be able to write the equivalent assembly language code for the accumulator machine or the load/store machine. Example hand assembly The opcodes for the load, sub, store, and halt instructions are 50, 30, 60, and 0, respectively. program symbol table executable word(a,5) a 0 5 word(b,a) b 1 0 label(x) x 2 label(y) y 2 load(a) 50 0 store(b) 60 1 halt 0 end(x) 2 program symbol table executable label(start) start 0 load(ten) 50 9 sub(ten) 30 9 store(data) 60 7 halt 0 word(data,five) data 7 8 word(five,5) five 8 5 word(ten,10) ten 9 10 end(start) 0