Clemson University -- CPSC 231 -- Fall 2009 SPARC - Scalable Processor ARChitecture load/store architecture - only load/store instructions can access memory 69 basic instructions (all fixed length - one word each = 32 bits) derived from RISC (Reduced Instruction Set Computer)work of David Patterson at Univ. of California at Berkeley designed for efficient pipelined implementation but the instruction set had some warts (e.g., no integer multiply, delayed branch) 32 registers (plus register windows) 8 global - %r0 == %g0 always returns zero 8 out \ 8 local > register windows allow previous outs to overlap current ins 8 in / Comparison and contrast of SPARC and Intel x86 (used in original IBM PC) similarities: 8-bit bytes (allows representation of ASCII-encoded character) byte-addressable memory (address down to individual character) two's complement for signed integers floating point follows IEEE standard arithmetic, logical, and shift operations branching and calling instructions condition codes used for branch decisions stack frame support (sp, fp/bp) for procedure calls can be pipelined and have superscalar, multithreaded, and multicore implementations differences: SPARC x86 (version 7) (8086) ----------- ------ introduced in 1986 introduced in 1978 (80386 in 1985) 32-bit words 16-bit words 32 general purpose registers 8 registers, most w/ special purpose (more on chip but only 32 (i.e., have fixed usage in certain are visible at any one time) operations) special register for multiplication AX and DX registers fixed usage in called Y multiplication fixed-length insts. (4 bytes) variable-length insts. (1-6 bytes) load-store architecture extended accumulator architecture, reg-to-reg ops reg-to-mem and mem-to-reg ops. string insts. with both operands in memory (movs, cmps, ...) 3-register instruction format: mainly 2-operand instruction format: rA op rB -> rC rA <- rA op memory memory <- memory op rA floating point uses separate set floating point uses a separate stack of 32 registers delayed branches normal branches RISC - reduced instruction set CISC - complex inst. set computer computer => streamlined for => complicated operations (some of ease of hardware implementation this is due to legacy, i.e., need for compatibility with previous 8080 and 8085 microprocessors) big-endian memory addressing little-endian memory addressing requires aligned operands unaligned operand access in hardware linear memory with paging segmented memory addressing two execution modes (OS, user) no protection memory-mapped I/O I/O instructions (IN, OUT) with port addresses for device registers extensions ---------- SPARC version 8 - multiply inst. 386 - 32-bit, 4 exec. modes, paging SPARC version 9 - 64-bit words 486 - heavily pipelined, on-chip FPU HyperSPARC - 2 insts./cycle Pentium - 2 insts./cycle, MMX SuperSPARC - 3 insts./cycle Pentium Pro, II, and III - 3 insts./ UltraSPARC - 4 insts./cycle cycle, out-of-order execution, SSE recent chips - SPARC64 series Pentium 4 HT - multithreaded from Fujitsu recent chips - Core, Core 2, i7 UltraSPARC T1, T2 - multithreaded (compatible chips have been produced by AMD and several other companies) getting information about a SPARC processor % uname -p sparc % psrinfo -v Status of virtual processor 0 as of: 02/11/2006 21:26:50 on-line since 02/05/2006 03:35:08. The sparcv9 processor operates at 650 MHz, and has a sparcv9 floating point processor. % psrinfo -vp The UltraSPARC-IIe physical processor has 1 virtual processor (0) % /usr/platform/sun4u/sbin/prtdiag System Configuration: Sun Microsystems sun4u Sun Blade 150 (UltraSPARC-IIe 650MHz) System clock frequency: 93 MHZ Memory size: 1GB ==================================== CPUs ==================================== E$ CPU CPU Temperature CPU Freq Size Implementation Mask Die Amb. Status --- -------- ---------- --------------------- ----- ---- ---- ------ 0 650 MHz 512KB SUNW,UltraSPARC-IIe 3.3 - - online note for SunOS on an x86, use /usr/platform/i86pc/sbin/prtdiag you can verify that an executable is a SPARC binary by using "file" when an executable has been compiled on SPARC: % file a.out a.out: ELF 32-bit MSB executable SPARC Version 1, dynamically linked, not stripped when an executable has been compiled on x86: % file a.out a.out: ELF 32-bit LSB executable 80386 Version 1, dynamically linked, not stripped, no debugging information available or when compiled on an Opteron: % file a.out a.out: ELF 64-bit LSB executable AMD64 Version 1, dynamically linked, not stripped, no debugging information available file also recognizes shell scripts: % file my_script my_script: executable shell script if you try to run an x86 executable on a SPARC machine, you should get this error message: i% ./a.out ./a.out: Exec format error. Binary file not executable. but I have also seen this error message when trying to run a SPARC executable on an Opteron system: % ./a.out ./a.out: Invalid argument. you can check what features are available using isainfo -v on sparc % isainfo -v 64-bit sparcv9 applications 32-bit sparc applications on opteron % isainfo -v 64-bit amd64 applications sse3 sse2 sse fxsr amd_3dnowx amd_3dnow amd_mmx mmx cmov amd_sysc cx8 tsc fpu 32-bit i386 applications sse3 sse2 sse fxsr amd_3dnowx amd_3dnow amd_mmx mmx cmov amd_sysc cx8 tsc fpu you can check the OS revision using showrev on sparc % showrev Hostname: shadow1.cs.clemson.edu Hostid: 832d2e37 Release: 5.9 Kernel architecture: sun4u Application architecture: sparc Hardware provider: Sun_Microsystems Domain: cs.clemson.edu Kernel version: SunOS 5.9 Generic 122300-08 May 2007 note on a Linux system, CPU info is available in the file /proc/cpuinfo